what are the semantics of yosys $alu and $macc cells?

I'd like to know if I can implement them with single bit full adders
and single bit mult cells only, or if I need additional primitives.
(trying to guess the semantics from the logic ops in their simulation
modules just makes my head hurt)
Reply to
Johann Klammer
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and what's those $lcu things (in techmap.v)
Reply to
Johann Klammer

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