Simplify handling of SW accessible registers in FPGA

Save lots of work
- Auto-generate register related code and documentation, and
- Keep SW, FPGA and Documentation synchronized
Register Wizard is now free :-)
Register Wizard is now released as a freeware to generate 'C' code, VHDL code and documentation from a single register definition file.
This allows a major efficiency boost for developing systems with software accessible registers, - and equally important - a simple way of keeping your Software, FPGA and Documentation synchronized.
The register definition file is written as normal text in the JSON file format. From this file you can automatically generate the following:
- 'C' header file for all registers and their addresses
- VHDL package for all registers and their addresses
- Full VHDL simple processor interface for register access
(May easily be wrapped to Avalon or AXI4-lite)
- Self-checking VHDL testbench for the processor interface
(Using UVVM Utility Library)
- Documentation in the form of a register map and register description
in the Office Open XML format for simple inclusion in MS Word.
This also means that specification changes are handled in a very structured manner - just by extending or modifying the register definition file and re-generating all the above.
The tool and usage is of course properly documented - including a tutorial and example, - and may be downloaded from our web-site:
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Enjoy :-)
And please send us feedback on potential improvements for your applications.
Reply to
Espen Tallaksen
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