Latest threads in Field-Programmable Gate Arrays

Vivado MIG says "Design entry" is VERILOG, how to change to VHDL?

With Vivado 2015.4, I'm trying to add DDR3 memory to a Microblaze design. I add the Memory Interface Generator to the b...

1 10yrs

spacewar

1 10yrs spacewar

Simplify handling of SW accessible registers in FPGA

Save lots of work - Auto-generate register related code and documentation, and - Keep SW, FPGA and Documentation synchr...

0 10yrs

espen.tallaksen

0 10yrs espen.tallaksen

CFP: 2016 Universal Technology Management Conference (UTMC) - USA

2016 Universal Technology Management Conference (UTMC) Bemidji State University, Minnesota, USA May 26-28, 2016 http://...

0 10yrs

sdiwc.org

0 10yrs sdiwc.org

How to define a counter whose width is big enough to hold integer 27?

Hi, I have a constant N = 27, how to define a counter whose width is big enough to hold integer 27? Or how to get a cons...

31 10yrs

wtxwtx

31 10yrs wtxwtx

Re: Call for Papers Reminder (extended): International MultiConference of Engineers and Computer Scientists (IMECS 2016)

Hey) My name is Tobias Casey. I am a freelance writer with more than 5 years of experience in content writing and blogg...

0 10yrs

caseytobb

0 10yrs caseytobb

Advanced VHDL Verification - Made simple - For anyone

VHDL testbenches very often need better structuring. We should strive for overview, modifiability, extendibility, maint...

0 10yrs

espen.tallaksen

0 10yrs espen.tallaksen

what are the semantics of yosys $alu and $macc cells?

I'd like to know if I can implement them with single bit full adders and single bit mult cells only, or if I need addit...

1 10yrs

klammerj

1 10yrs klammerj

Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea

Graduate Research Assistantship at the Department of Computer Engineering, Hallym University, Gangwon-do, Korea The Emb...

0 10yrs

jeonggun.Lee

0 10yrs jeonggun.Lee

VQ44 recommended footprint

The Xilinx packaging documentation for the VQ44/VQG44 package (document PK0 12, v1.2, dataed 2004-06-18) doesn't contai...

2 10yrs

spacewar

2 10yrs spacewar

How do I instantiate an FGEN instance for Atmels Figaro IDS in EDIF?

Specifically it's about how to specify the function to implement in the FGEN instance. this I have as the cell definiti...

1 10yrs

klammerj

1 10yrs klammerj

Sending multiple MSI interrupts via Xilinx "AXI Memory Mapped to PCIe" core

Hi, I wanted to prepare a small IP core able to serialize multiple interrupts as MSI interrupts handled by the Xilinx A...

2 10yrs

wzab01

2 10yrs wzab01

Where is a code example on how to use a floating multiplier on FPGA for VHDL-2008?

Hi, I need a full code example on how to use a floating multiplier on FPGA for VHDL-2008. What is the document name fro...

8 10yrs

wtxwtx

8 10yrs wtxwtx

Synplify Identify with Microsemi FPGAs

Is anybody out there using Microsemi's Libero SoC and the bundled Synplfiy Identify? Identify is giving me problems: 1....

1 10yrs

93907

1 10yrs 93907

EPM240T100C5N, LM2596, USB Blaster.

How to make it visible in QuartusII ? Pinout cpld ? How to solder it to pcb ? Links ?

2 10yrs

emailbogsuv

2 10yrs emailbogsuv

Source control and ip cores

I'm looking for a peace of advice. Currently I use git for version control in my VHDL projects and I usually i nclude a...

15 10yrs

stebanoid

15 10yrs stebanoid

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