Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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watermarking on FPGA
I'm going to do a very simple watermarking. I want to embed a signature on unused LUTs. could you please tell me how I can do it? Thank you very much.
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8 years ago
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Freelance engineer in barcelona area
We are looking for a freelance engineer in barcelona area. Please contact to my e-Mail.
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8 years ago
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Altera MAX10 image capture application
We are interested in finding someone to help develop an FPGA image capture application. We are using Altera's MAX10 FPGA and Arrow's BeMicro MAX10 dev elopment board. The image sensor is the MT9V034....
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8 years ago
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Fully preposterous gate arranger
Is there synthesis software out there that'll take Verilog or other HDL and generate a netlist of 7400-series logic? To carry things one step further, if you were seriously contemplating such a thing,...
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8 years ago
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Opinions, on this newfangled thing, please
I just ran across this: It looks like it could be a nifty thing to use in certain circumstances, particularly where one needs a complicated analog block in little space with fairly high bandwidth...
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8 years ago
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hamsterworks + lauriVosandi + X = Error
Hello i am new in vhdl, but try it, I want to make pipe between OV7670 and monitor, best thing is to use code o f Hamsterwork's with Lauri's edition and pt it to ML402 for Virtex-4 XC4VSX35, it...
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8 years ago
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Programming waveshare core3s250e with Impact and ISE 14.1
Folks, Sorry if this is off-topic. I have a project that uses the above board, which has an Spartan 3E chip and an EEPROM for holding the config. If I load Impact on its own I can program the prom,...
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8 years ago
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FPGA for a beginner
I know this subject is very repetitive, but It's very confusing to me. I'm familiar to verilog coding and digital circuit designing but I haven't work with FPGAs. I want to learn it. could you please...
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8 years ago
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modulo 2**32-1 arith
Hello. I need to add two unsigned numbers modulo 2**32-1. Now it's done in very inefficient way: at first clock cycle there is simple addition of two 32-bit unsigned numbers with 33-bit result and on...
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8 years ago
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Error in converting code to VHDL
Hi, Can some one please help I am trying to convert below code to VHDL using HDL Coder but getting error .Please can you have a look on it and see whats the mistake in block diagram. x1=[1 2 3 4 5 6 7...
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8 years ago
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Simulation vs Synthesis
So I have a partly-complete design for a 6502 CPU, it's simulating just fin e for the implemented opcodes, but when I run synthesis, I get a whole load of "Sequential element ( ewSPData_reg[23] ) is...
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8 years ago
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problem with impact
Hello friends I have a fpga spartan-3 development board that only has a parallel port for JTAG. I used a parallel to usb cable and connected it to my laptop. When i connect the board to laptop,...
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8 years ago
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Nandland Go Board - Your FPGA Playground
There's a new FPGA development board on Kickstarter. It's called the Nandl and Go Board, and it aims to be an inexpensive, easy-to-use FPGA developmen t board to learn about how FPGAs work and what...
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8 years ago
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ERROR:HDLParsers:409 .... at left hand side. Please help
Dear all, I am very new in vhdl, can anybody tell me what problem, following is code : disp_ena : OUT STD_LOGIC; --) column : OUT INTEGER; -- row : OUT INTEGER;:...
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8 years ago
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ERROR:MapLib:30 - LOC constraint P11 on vga_b_out<1> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
Dear all first of all want thanx to everyone who belong to this forum and give help to each other. I use Xilinx ISE 14.7, and ML405 I checked ML405's schematic that pins, and are exist,i used advise...
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8 years ago
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