Field-Programmable Gate Arrays

Active HDL Generic Controls

I am working with Active HDL and I'm pretty sure in the past I was able to set generics at the top level from within th...

5 comments posted 10yrs

posted by gnuarm

5 comments posted 10yrs posted by gnuarm

comparing hardware architecture

Currently, I have two algorithm to consider. one using FFT, one using DCT the DCT is using NEDA for FFT, I am not quite...

2 comments posted 10yrs

posted by user123random

2 comments posted 10yrs posted by user123random

Give God your all (live true faith)

Give God your all (live true faith): As the world dives deeper and deeper into self-absorption, seek your path from the...

9 comments posted 10yrs

posted by rick.c.hodgin

9 comments posted 10yrs posted by rick.c.hodgin

Advice to a newbie

I a retired person with limited resources and I've always been interested in CPU design, so now that I have time I want...

53 comments posted 10yrs

posted by cbayona

53 comments posted 10yrs posted by cbayona

Article - Extinction Level Event

http://www.xess.com/blog/extinction-level-event/ The synopsis of the guy's argument is: Given Intel bought Altera, and...

4 comments posted 10yrs

posted by rgaddi

4 comments posted 10yrs posted by rgaddi

Explicitly setting a variable to undefined

Hello, my question is probably best explained on a piece of code (the snippet is V erilog, but the question should be m...

27 comments posted 10yrs

posted by minexew

27 comments posted 10yrs posted by minexew

VHDL BFMs and VVCs for AXI4-Lite, Avalon-MM, UART, I2C and SPI - for free - and open source

UVVM - the new VHDL verification methodology is a very good way to structur e your VHDL testbenches - and to make easil...

0 comments posted 10yrs

posted by espen.tallaksen

0 comments posted 10yrs posted by espen.tallaksen

Where do you want to go for eternity?

I saw this video today on the ComputerHistory channel on YouTube. The man cited, David Cutler, has been a pioneer in se...

0 comments posted 10yrs

posted by rick.c.hodgin

0 comments posted 10yrs posted by rick.c.hodgin

A flawless execution

At the cross, Jesus took our filthy shame, and exchanged it for His spotless righteousness. No penalty. No condemnation...

3 comments posted 10yrs

posted by rick.c.hodgin

3 comments posted 10yrs posted by rick.c.hodgin

Multi-port memory

In this article http://fpga.org/wp-content/uploads/2016/05/grvi_phalanx_fccm2016.pdf on the second page there's a descr...

19 comments posted 10yrs

posted by stebanoid

19 comments posted 10yrs posted by stebanoid

Recoding openCV C++ project in pure verilog

I have a 6 month project to work with by hand-recoding openCV C++ project into pure RTL for FPGA usage. I have a Xilinx...

2 comments posted 10yrs

posted by user123random

2 comments posted 10yrs posted by user123random

Constraining data to out-of-phase clocks

I've got a project coming up in which one of the things I'm going to need to do is take in the 1 PPS output from a GPS...

19 comments posted 10yrs

posted by rgaddi

19 comments posted 10yrs posted by rgaddi

Problem if compilation order in OOC compilations in Xilinx Vivado

Hi, Has anybody in this group faced the problem of incorrect compilation order of blocks selected for Out-of-context (O...

3 comments posted 10yrs

posted by wzab01

3 comments posted 10yrs posted by wzab01

FPGA boards in egypt

Plz I want to buy FPGA boards for my graduation project and l don't know where can I get it from Egypt (FPGA spartan 6 s...

5 comments posted 10yrs

posted by aymanmimomimomimo

5 comments posted 10yrs posted by aymanmimomimomimo

Problem with AXI4 Lite in Cyclone V

Hi, I have created a simple AXI4-Lite slave, which works perfectly in Xilinx Zynq FPGA. Unfortunately, the same design...

6 comments posted 10yrs

posted by wzab01

6 comments posted 10yrs posted by wzab01