Field-Programmable Gate Arrays

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Lattice Diamond and VHDL-2008

I don't have any trouble getting the simulation (Active HDL) or synthesis (Synplify) tools to work with VHDL-2008, but...
6 comments posted 10yrs
posted by gnuarm
6 comments posted 10yrs posted by gnuarm

Active HDL Generic Controls

I am working with Active HDL and I'm pretty sure in the past I was able to set generics at the top level from within th...
5 comments posted 10yrs
posted by gnuarm
5 comments posted 10yrs posted by gnuarm

comparing hardware architecture

Currently, I have two algorithm to consider. one using FFT, one using DCT the DCT is using NEDA for FFT, I am not quite...
2 comments posted 10yrs
posted by user123random
2 comments posted 10yrs posted by user123random

Give God your all (live true faith)

Give God your all (live true faith): As the world dives deeper and deeper into self-absorption, seek your path from the...
9 comments posted 10yrs
posted by rick.c.hodgin
9 comments posted 10yrs posted by rick.c.hodgin

Advice to a newbie

I a retired person with limited resources and I've always been interested in CPU design, so now that I have time I want...
53 comments posted 10yrs
posted by cbayona
53 comments posted 10yrs posted by cbayona

Article - Extinction Level Event

http://www.xess.com/blog/extinction-level-event/ The synopsis of the guy's argument is: Given Intel bought Altera, and...
4 comments posted 10yrs
posted by rgaddi
4 comments posted 10yrs posted by rgaddi

Explicitly setting a variable to undefined

Hello, my question is probably best explained on a piece of code (the snippet is V erilog, but the question should be m...
27 comments posted 10yrs
posted by minexew
27 comments posted 10yrs posted by minexew

Where do you want to go for eternity?

I saw this video today on the ComputerHistory channel on YouTube. The man cited, David Cutler, has been a pioneer in se...
0 comments posted 10yrs
posted by rick.c.hodgin
0 comments posted 10yrs posted by rick.c.hodgin

A flawless execution

At the cross, Jesus took our filthy shame, and exchanged it for His spotless righteousness. No penalty. No condemnation...
3 comments posted 10yrs
posted by rick.c.hodgin
3 comments posted 10yrs posted by rick.c.hodgin

Multi-port memory

In this article http://fpga.org/wp-content/uploads/2016/05/grvi_phalanx_fccm2016.pdf on the second page there's a descr...
19 comments posted 10yrs
posted by stebanoid
19 comments posted 10yrs posted by stebanoid

Recoding openCV C++ project in pure verilog

I have a 6 month project to work with by hand-recoding openCV C++ project into pure RTL for FPGA usage. I have a Xilinx...
2 comments posted 10yrs
posted by user123random
2 comments posted 10yrs posted by user123random

Constraining data to out-of-phase clocks

I've got a project coming up in which one of the things I'm going to need to do is take in the 1 PPS output from a GPS...
19 comments posted 10yrs
posted by rgaddi
19 comments posted 10yrs posted by rgaddi

FPGA boards in egypt

Plz I want to buy FPGA boards for my graduation project and l don't know where can I get it from Egypt (FPGA spartan 6 s...
5 comments posted 10yrs
posted by aymanmimomimomimo
5 comments posted 10yrs posted by aymanmimomimomimo