Field-Programmable Gate Arrays - Page 89

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• 03-04-2007
• Large power planes vs. power islands vs. slits for decoupling   [ 2 ]
• • Marc Battyani
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• 03-04-2007
• Call for papers on Hardware Architectures for Genetic, Neural and Fuzzy Systems
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• 03-04-2007
• EDK 8.1i : add port for component
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• 3

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• 03-04-2007
• regarding power and timing
• • ram
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• 03-04-2007
• CUDD
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• 1

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• 03-03-2007
• Boot uClinux from RAM without flash
• • Lancer
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• 03-03-2007
• Multiplication operation
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• 03-03-2007
• V.34 Modem IP core
• • GX
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• 03-03-2007
• New modelsim PE student edition 6.2g and Xilinx ISE 9.1i User Linking problems
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• 03-03-2007
• DRP of the Virtex 5 PLL
• • Sylvain Munaut
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• 0

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• 03-02-2007
• Sources (products) for Cannibalizing FPGAs, PLDs, etc.
• • msg
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• 7

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• 03-02-2007
• help read a pixel for picture
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• 03-02-2007
• Instance Name Being Removed?
• • Brandon Jasionowski
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• 5

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• 03-02-2007
• XST ucf timespec
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• 1

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• 03-02-2007
• OPB-to-PLB bridge
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• 1

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• 03-02-2007
• How to connect an IP to OPB bus??
• • Sandip
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• 2

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• 03-01-2007
• Virtex-5 are available from distribution
• • Peter Alfke
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• 0

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• 03-01-2007
• What is the running frequency for a typical FPGA application using Virtex 5
• • Weng Tianxiang
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• 2

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• 03-01-2007
• Help with Partial Reconfiguration on Spartan3
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• 1

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• 03-01-2007
• apologia
• • Austin Lesea
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• 2

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• 03-01-2007
• suggestions for good MPEG encoder dev kit, embedded hard disk dev kit
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• 03-01-2007
• xilinx block ram synthesis
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• 12

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• 03-01-2007
• looking for the source VHDL for Jpeg 2000
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• 03-01-2007
• Xilinx ISE Webpack 9.1 RTL schematic viewer problem
• • Robert Ganter
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• 03-01-2007
• Bypass caps, X2Y and 'puddles'.
• • Symon
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• 11

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• 03-01-2007
• XPS (NGCBUILD) fails when creates netlist: "failed to copy to implementation"
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• 03-01-2007
• google tech talks : "General Purpose, Low Power Supercomputing Using Reconfiguration"
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• 03-01-2007
• what about dma scatter /gather support in xilinx edk ipif ?
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• 03-01-2007
• Regional Clock Network and Large Designs
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• 3

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• 03-01-2007
• Where can i get free CAN VHDL core
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• 4

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• 02-28-2007
• what does a 'blank check' do exactly
• • mtsukanov
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• 14

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• 02-28-2007
• Altera Byte Blaster Cable on Linux
• • B. Joshua Rosen
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• 02-28-2007
• Xilinx USB flatform cable length mistery ?
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• 02-28-2007
• Can write, can't read with OPB_SPI 1.00e
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• 02-28-2007
• SCons build tool as an alternative to makefiles
• • Patrick Dubois
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• 15

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• 02-28-2007
• Virtex 4 FX Sonet Alignment
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• 6

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• 02-28-2007
• PCI-E TS1s
• • Fred
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• 4

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• 02-28-2007
• How to implement pipeline in this case?
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• 3

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• 02-28-2007
• Spartan MicroBlaze
• • Rob
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• 02-28-2007
• [Q] Xilinx Webpack warning message "Cannot apply TIMESPEC TS_WR_CPLD"
• • heliboy2003
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• 1

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• 02-27-2007
• Altera PowerPlay Power estimation
• • AG
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• 1

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• 02-27-2007
• ISE:Simulation
• • ANIL CELEBI
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• 1

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• 02-27-2007
• How can we know how many BRAM are used?
• • lkjrsy
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• 1

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• 02-27-2007
• Handel-C, multiple clock domains, and PAL library
• • Pawel Piotr Czapski, SP5EPD
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• 0

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• 02-27-2007
• Xilinx and archive of Teaching Materials
• • Pawel Piotr Czapski, SP5EPD
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• 0

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• 02-27-2007
• Modelsim (errno = ENOSPC) error
• • robquigley
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• 02-27-2007
• $recovery
• • skyworld
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• 4

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• 02-27-2007
• spartan 3E USB port... use for i/o instead of programming
• • aiiadict
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• 2