Hi I was using 'define in my verilog file, while trying to compile the code using Xilinx ISE 7.1 I was getting error ?
Could anyone please help me in this regard
Rgds bijoy
FPGA :'define not allowed in ISE ?
Aug 16, 2007
1 Replies
using Xilinx ISE 7.1 I was getting error ?
`define or 'define? Make sure you're using the correct tick.
Also, please post the exact error message it gave, and any code that might come before the error.
Cheers, Jon
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