Field-Programmable Gate Arrays

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Xilinx / ISE multi-cycle path constraint pitfall

Hello, To summarize the issue briefly: I have a group of flip-flops which toggle every 4 clocks by using an "clock enab...
26 comments posted 19yrs
posted by eli.billauer
26 comments posted 19yrs posted by eli.billauer

DDR controller - best device to perform

Hello I decided to make my own DDR controller. I want to do this on CycloneII or Spartan-3 I'm not decided yet. That's...
16 comments posted 19yrs
posted by "SwietyMikolaj["
16 comments posted 19yrs posted by "SwietyMikolaj["

help on camera ports

i have a posted for a camera and i was suggesed the following. it is 1/3 Color Camera Mod C3188A-6018 Digital output.i...
1 comments posted 19yrs
posted by srimankk
1 comments posted 19yrs posted by srimankk

Xilinx Constraints Question

Hello group, We are modelling our ASIC in an FPGA (Spartan) for system testing and as a demonstrator. For power reasons...
4 comments posted 19yrs
posted by moogyd
4 comments posted 19yrs posted by moogyd

Minimal power?

Hello, How feasible is it to shut down (or place in low power mode) an fpga (eg. XC3S1000 from Xilinx or similar) and p...
4 comments posted 19yrs
posted by amerdsp
4 comments posted 19yrs posted by amerdsp

Actel APA1000 and JTAG

Hi all, We are trying to programme a FLASH memory linked to a APA1000. However, we have a data-blaster that should prog...
2 comments posted 19yrs
posted by kev.parsons
2 comments posted 19yrs posted by kev.parsons

Slice equation in bitstream

hey, in FPGA-Editor i can choose a slice and type in an equation for this block. i need information, where i can find t...
14 comments posted 19yrs
posted by lembke.stefan
14 comments posted 19yrs posted by lembke.stefan

FIFO16 on virtex4 error?

I am currently using FIFO16 with xilinx Virtex-4. I found out in my design, the "almostempty" "almostfull" "empty" "ful...
4 comments posted 19yrs
posted by ssc3k
4 comments posted 19yrs posted by ssc3k

Reconfiguring a Virtex4 DCM_ADV.

Hi All, From reading UG071, part of the Virtex4 user guide, I see that I can reconfigure the CLKFX_MULTIPLY and CLKFX_D...
3 comments posted 19yrs
posted by symon_brewer
3 comments posted 19yrs posted by symon_brewer

Routing JTAG pins thru FPGA

Hi, This is my first post to this group. I am an FPGA newbie trying to learn this new and exciting stuff. I have a set...
3 comments posted 19yrs
posted by vu3rdd
3 comments posted 19yrs posted by vu3rdd

FPGA :'define not allowed in ISE ?

Hi I was using 'define in my verilog file, while trying to compile the code using Xilinx ISE 7.1 I was getting error ? C...
1 comments posted 19yrs
posted by pbijoy
1 comments posted 19yrs posted by pbijoy

Scilab / Matrix

Hi all, I need to implement a SCILAB matrix code into a FPGA (vhdl or verilog code , use dsp block, or any others solut...
1 comments posted 19yrs
posted by bhb22l
1 comments posted 19yrs posted by bhb22l

MGT Link

Hi I am designing two boards with virtex 4 fx devices fitted. They will stac one on top of the other using a board to b...
4 comments posted 19yrs
posted by maxascent
4 comments posted 19yrs posted by maxascent