Hi All, From reading UG071, part of the Virtex4 user guide, I see that I can reconfigure the CLKFX_MULTIPLY and CLKFX_DIVIDE attributes on-the-fly using the DCM's dynamic reconfiguration port. Very nice.
My question is this. Can I use this port to reconfigure the CLKDV_DIVIDE attribute on-the-fly, and if so, how? I couldn't find a reference to this in the document.
For background, I have a >500MHz clock coming into the part which I divide by two using the DCM's CLKIN_DIVIDE_BY_2 feature. It would be nice and easy if I could use the DRP to change the divide ratio of the signal at CLKDV. It's no big deal if I can't as I could always do this programmable division in the fabric, but the DRP would make things neater.
Cheers, Syms.