Field-Programmable Gate Arrays

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OCM BRAM and PCC issues...

Hello All, I am using Virtex II pro for a design with PPC,Timer, Bram, OCM, PLB,OPB. The Bram is attached on the OCM bu...
0 comments posted 19yrs
posted by lastval
0 comments posted 19yrs posted by lastval

DDR2 controller V4 vs V5 differences ?

Hi, I've been working on Virtex 4 with a DDR2 controller for about 1 year now and it works fine. The controller is base...
6 comments posted 19yrs
posted by SomeOne
6 comments posted 19yrs posted by SomeOne

Speed test between FPGA and DSP or PC.

Hi, I would like to make a test in which I try to prove the differences in speed between DSPs and FPGAs. The test could...
3 comments posted 19yrs
posted by pbantunez
3 comments posted 19yrs posted by pbantunez

Inout ports in EDK

Hello everybody, I am having trouble incorporating a inout port of my custom peripheral in EDK. I found that the wrappe...
0 comments posted 19yrs
posted by koustav79
0 comments posted 19yrs posted by koustav79

Annoying

Hi all, Am I the only one who finds the digital magazine subscription of Xcell Journal very annoying? Is there a place...
7 comments posted 19yrs
posted by christian
7 comments posted 19yrs posted by christian

ROUTING=CLOSED in Xilinx 9.1 PR tools

I want to build a reconfigurable region that has no static routing inside. In the 8.2 version of the tools this was pos...
2 comments posted 19yrs
posted by jasuris
2 comments posted 19yrs posted by jasuris

Altera DDR Controller, Modelsim and Verilog

Hi Forumees, Anyone have any experience simulating the verilog model of the DDR SDRAM Controller in modelsim? I am tryi...
0 comments posted 19yrs
posted by fpgabuilder-groups
0 comments posted 19yrs posted by fpgabuilder-groups

ML365

Hi Does anyone know where I can get a copy of the gerber files for the ML36 board? cheers Jon
0 comments posted 19yrs
posted by maxascent
0 comments posted 19yrs posted by maxascent

xilinx usb cable question

Hi, Does anybody have any luck with running the Xilinx usb-cable driver on a Linux 64 system? I'm having severe problem...
4 comments posted 19yrs
posted by tralalal
4 comments posted 19yrs posted by tralalal

comparison with embedded processor

Hi all, I need to implement this code (below) with a embedded processor FPGA. Do you have any information to help me in...
5 comments posted 19yrs
posted by bhb22l
5 comments posted 19yrs posted by bhb22l

how to bidirectional signal in xilinx EDK tool ?

hi all i am facing a problem with EDK tool. can you please assist me in this regard.the problem is :- i am using a top...
2 comments posted 19yrs
posted by kmk1978
2 comments posted 19yrs posted by kmk1978

Burst Memory Transfer Request from PPC

hi all, I'm working on the ML310 board, using EDK8.2i. I'd like to know how can we write c codes that executes burst da...
1 comments posted 19yrs
posted by my25050
1 comments posted 19yrs posted by my25050

Power Reduction Strategy

I have a design on a Spartan 3 2000. It uses nearly all slices, two thirds of the FF and LUTs. Also all BlockRam and al...
12 comments posted 19yrs
posted by tgschwind
12 comments posted 19yrs posted by tgschwind