synthesis showing warning (replicated 1 time(s) to handle iob=true attribute.)

hi i am designing ahb arbiter . In which i am using hmaster_lock as output signal . when i am doing synthesis on xilinx 6.3 it is giving warning

WARNING: FlipFlop hmaster_lock has been replicated 1 time(s) to handle iob=true attribute.

pls help me why this warning is comming

thanks ankur

Reply to
ankur
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hi i am designing ahb arbiter . In which i am using hmaster_lock as output signal . when i am doing synthesis on xilinx 6.3 it is giving warning

WARNING: FlipFlop hmaster_lock has been replicated 1 time(s) to handle iob=true attribute.

pls help me why this warning is comming

thanks ankur

Reply to
ankur

It is generally safe to ignore these warnings. All this says that there are now two flip-flops in the part where there was only one in the design. The second (replicated) flip-flop is in the IOB (input output block) to meet the constraint "iob=true". Possibly the state of "hmaster_lock" is used internally to the FPGA as well as at the pin. In this case the flip-flop internal to the FPGA (in a slice) is used for internal feedback, while the flip-flop in the IOB only feeds the pin.

If the D input to the flip-flop that creates the "hmaster_lock" signal uses only sources synchronous to its clock, there is no problem replicating the flip-flop. If for some reason you have an asynchronous signal feeding the D of the flip-flop, you can have a problem where the two flip-flops don't agree after their input changes within the setup/hold window. This is why the warning is issued.

If "hmaster_lock" is not a signal that you generated yourself, i.e. it's part of a module you included, you probably don't need to worry about the warning. If you generate this signal check that the logic that creates it is synchronous.

Other than replicating the signal yourself, which would make the source less readable and easier to break if you change it, there is no way to avoid the warning message. If you upgrade to a new version of ISE (which I normally would not recommend if you have a working project) you can filter the warnings so you don't need to re-visit them each time you re-build.

HTH, Gabor

PS - Warnings are not "errors", although they often help you to find mistakes in your design. If you work with FPGA's you should get used to the fact that it is not reasonable to expect a design to compile entirely without warnings.

Reply to
Gabor

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