Routing JTAG pins thru FPGA


This is my first post to this group. I am an FPGA newbie trying to learn this new and exciting stuff.

I have a set of 3 boards from an amateur radio project. Board #1 is a back plane where board #2 and #3 plugs in.

Board #2 has a Cypress FX2 chip and a Altera Cyclone II FPGA. Board #3 has a Max-II based CPLD.

I would like to download Max-II configuration thru the FX2. For that I am trying to use kawk's excellent usb-blaster emulation code:

formatting link

I route the FX2 port B pins 0..3 which are emulating TDI, TDO, TCK and TMS pins as shown in Variant-A in the above webpage. These pins go into the FPGA (cyclone-II) on board #2. Inside the FPGA, these are routed to some lines shared thru the backplane to the board #3, which are routed to the CPLD JTAG pins.

To accomplish this, I load a simple code into the Cyclone II on board #2, which simply 'assigns' the appriate input pins to the output (TDI, TCK, TMS are taken as input from port B and output into relevant I/O pins into board #3 thru the backplane, TDO is taken from board #3, and simply assigned to the appropriate pin of port B). After loading this FPGA configuration, I load the FX2 code built from the above webpage.

Windows recognize the FX2 at this point as USB-Blaster and I pointed it to the right drivers. Quartus also recognize it as USB-Blaster. But when it tries to scan for devices, it finds none! i.e. the routing of JTAG pins thru the FPGA does not seem to be working fine.

Is there anything special I need to do inside the FPGA code? I am pasting the FPGA routing code here.

// B0 - TDI // B1 - TDO // B2 - TCK // B3 - TMS // A23 - Atlas TMS - output // A24 - Atlas TCK - output // A27 - Atlas TDO - input // A29 - Atlas TDI - output

module usb_blaster_emulation( B0, B1, B2, B3, A23, A24, A27, A29 );

input B0; output B1; input B2; input B3;

output A23; output A24; input A27; output A29;

assign A23 = B3; assign A24 = B2; assign B1 = A27; assign A29 = B0;


I haven't done too much of FPGA work. I would very much appreciate any help in finding the mistake in the above setup. Thanks


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Have you got your TDO and TDI connections right? TDO of one device normally drives TDI of another. I'm not saying it's wrong; but your comment against A27 above is confusing.

Do you need pull-ups?

Reply to
Andrew Holme

I am actually not chaining devices. I am using FPGA on one board to route the JTAG emulation pins into the JTAG pins of an FPGA sitting on another board.

Yes, I have the pull ups in place.

Thanks Ramakrishnan

Reply to

Please check these points...

  1. Signal routing distance between Board2 Cyclone II FPGA & Borad3 Max II CPLD.
  2. TDI pins of Microcontroller(Port pin) & MAX II CPLD should have have pull up resistors.
  3. Microcontroller TDI should be MAX II CPLD TDO and Microcontroller TDO should be MAX II CPLD TDI.

I think Andrew point is correct. Because TDO of Microcontroller should drive TDI of MAX II CPLD.

Regards, JK

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