Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Tristate bus on spartan FPGA
Hi, im implementing a 16bit bus along the lines of AMBA APB for some of my peripherals like IDE ATA controller, LCD dsplay controller, ftdi usb interface etc. But i found that xilinx spartan devices...
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16 years ago
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Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
Hi - Can someone point me to where FVAL, LVAL, DVAL relationship requirements are? I look at the i/f spec on but it doesn't list any. I'm looking for something like After FVAL goes valid, LVAL should...
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16 years ago
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Virtex-4 SELECT MAP configuration
Hi Let me ask two questions --: According to Virtex-4 configuaration guide ( interface is either 8-bit or 32-bit, with up to 60MHz CCLK. Most of diagrams and explanations are based on 8-bit interface....
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16 years ago
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Directing data to DDR
Hi all, I'm a newbie in this area. I'm working on a custom board that has Virtex-4 on it and doing my development using XPS. What I'm trying to do is moving some data that's coming into my peripheral...
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16 years ago
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Altera / Lattice / Xilinx CPLDs ?
Hi We are searching a small CPLD gate count like a coolrunner 128. - Two IO banks 1.4V to 3.3V with 5V tolerant - VCC should be 3.3V or 1.8V The 5V tolerant is important ! Volume : 5000 - 10000 pces...
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16 years ago
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ECP2/M und Serdes
Hello, do have anyone expierence with the SERDES in the lattice ECP2/M family? bye martin sauer
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16 years ago
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global clock on virtex5 question
Hi to everybody, I'ts not very clear from the Virtex 5 User guide, Clock resources chapter if it's possible to route (on different GCLK inputs) single ended and differential CLKs. Then at...
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16 years ago
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Unexplained behavior with DDR2 controller on Xilinx V5
Hi, I'm working on a custom DDR2 controller on Virtex 5 and I have a very weird behavior that I can't explain. I'm doing my tests on a SO-DIMM of which I only use 8 bits and running it at 200 MHz. My...
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16 years ago
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ASAP 2008: Preliminary Call for Papers
============================================================================================= Dear colleague, Please accept our apologies if you recieve multiple copies of this CFP....
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16 years ago
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Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
Hi, I would like to pose an interesting guess topics for experienced engineers: What is the largest number of state machines in a current chip design: 1k, 10k or ... I have finished 8 projects and...
20
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16 years ago
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[ANNOUNCE] YARDstick - custom processor development toolset
Dear friends, I am very pleased and proud to announce YARDstick ( a custom processor development toolset with an impressive list of features. YARDstick is a novel design automation tool for custom...
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16 years ago
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FPGA power optimize! Help
Hi I recently have designed some simple FPGA application. Now i need research on optimizing power in FPGA design. I have found many document but none of them are in detail. I need free document and...
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16 years ago
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sounds
hello to everyone, im a newbie in using spartan 3e kit...Is it possible for the spartan 3e kit to store an audio sounds like wav file or mp3 file?
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16 years ago
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XAPP806 issues DCM Phase Shift
Hello, I'm trying to hash through application XAPP806 "Determining the Optimal DCM Phase Shift for the DDR Feedback Clock" as an exercise in MicroBlaze, EDK, BSB, Platformw Studio, XPS, whatever....
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16 years ago
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Virtex II pro design question
Hi, In a Virtex II pro design operating at 250 MHz, the FPGA interfaces to an ADC, does some preliminary signal processing, and transmits data to a DSP upon having filled a local buffer with data. The...
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16 years ago
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