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Virtex II pro design question

Hi,

In a Virtex II pro design operating at 250 MHz, the FPGA interfaces to an ADC, does some preliminary signal processing, and transmits data to a DSP upon having filled a local buffer with data. The FPGA is the lowest speed grade in the family and I've been tasked with making the design works no matter what. Our data with is 10 bits.

Part of a detection criteria, samples have to be screened before being admitted to further processing. This involves making sure that data is above certain threshold. Now, right in the middle of the dynamic range of the sample width, when I subtract the threshold value from that sample, a momentary glitch appear on the tenth bit making it impossible to tell whether the difference is positive or negative. Because the sampled data corresponds to physical entity that is naturally limited in bandwidth, this transition of sign occurs rather smoothly. Thus I managed to butcher my way through by omitting thresholding on this very case in which a reversal of sign occurs. The caveat obviously is not logging this particular transition sample.

So though the design works for now, I was wondering whether there exists a more elegant/clever solution around this.

Many thanks,

-Mani

Reply to
Manny
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If you see glitches, you probably omitted a register stage somewhere. You need to make sure you have the IOB FFs on the DAC data bus, you need another set of FFs on this input path within your threshold detection block, yet another for your block's output and you would probably do well to break your substraction in two or three pipelined stages since 250MHz is pretty tight for V2P.

A glitch on the 10th bit indicates that the carry chain is a little too slow/long for your target operating period so you need to pipeline this subtraction at least one step further than you may already have.

Since you did not describe your design's structure, I have no idea how much of this you have already done.

Reply to
Daniel S.

I've already done that. Obviously the logic requires two clock cycles for thresholding immediately when the 10th bit changes sign, which means that the first sample is missed. This isn't terribly bad as the slow physical pluse has enough samples in the rising edge to get caught properly.

Thanks for the input Daniel, just wanted to make sure that I'm approaching this in the right way.

I don't know why would people want to use v2pro these days. Managers usually decide on the system's components and we have to live with the consequences of that.

Regards,

-Manny

Reply to
Manny

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