Field-Programmable Gate Arrays

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Virtex-4 SELECT MAP configuration

Hi Let me ask two questions --: According to Virtex-4 configuaration guide (http://www.xilinx.com/bvdocs/userguides/ug0...
1 comments posted 18yrs
posted by pasacco
1 comments posted 18yrs posted by pasacco

Directing data to DDR

Hi all, I'm a newbie in this area. I'm working on a custom board that has Virtex-4 on it and doing my development using...
0 comments posted 18yrs
posted by smayadewi
0 comments posted 18yrs posted by smayadewi

Altera / Lattice / Xilinx CPLDs ?

Hi We are searching a small CPLD gate count like a coolrunner 128. - Two IO banks 1.4V to 3.3V with 5V tolerant - VCC s...
10 comments posted 18yrs
posted by laurent.gauch
10 comments posted 18yrs posted by laurent.gauch

ECP2/M und Serdes

Hello, do have anyone expierence with the SERDES in the lattice ECP2/M family? bye martin sauer
0 comments posted 18yrs
posted by msauer
0 comments posted 18yrs posted by msauer

global clock on virtex5 question

Hi to everybody, I'ts not very clear from the Virtex 5 User guide, Clock resources chapter if it's possible to route (o...
4 comments posted 18yrs
posted by piclist9
4 comments posted 18yrs posted by piclist9

ASAP 2008: Preliminary Call for Papers

============================================================================================= Dear colleague, Please ac...
0 comments posted 18yrs
posted by j4murali
0 comments posted 18yrs posted by j4murali

FPGA power optimize! Help

Hi I recently have designed some simple FPGA application. Now i need research on optimizing power in FPGA design. I hav...
0 comments posted 18yrs
posted by embeddedexpert2007
0 comments posted 18yrs posted by embeddedexpert2007

sounds

hello to everyone, im a newbie in using spartan 3e kit...Is it possible for the spartan 3e kit to store an audio sounds...
2 comments posted 18yrs
posted by carlmorada
2 comments posted 18yrs posted by carlmorada

XAPP806 issues DCM Phase Shift

Hello, I'm trying to hash through application XAPP806 "Determining the Optimal DCM Phase Shift for the DDR Feedback Clo...
0 comments posted 18yrs
posted by bradsmallridge
0 comments posted 18yrs posted by bradsmallridge

Virtex II pro design question

Hi, In a Virtex II pro design operating at 250 MHz, the FPGA interfaces to an ADC, does some preliminary signal process...
2 comments posted 18yrs
posted by mloulah
2 comments posted 18yrs posted by mloulah

Beginner Advice (Languages, tools etc.)

Hi, Please excuse me for sounding like I don't have a clue what I'm talking about. I am here because I want to learn. I...
13 comments posted 18yrs
posted by rl
13 comments posted 18yrs posted by rl