global clock on virtex5 question

Hi to everybody,

I'ts not very clear from the Virtex 5 User guide, Clock resources chapter if it's possible to route (on different GCLK inputs) single ended and differential CLKs. Then at configuration time use either the single ended clock (routed at the P side of the differential input pair) or differential clock (say LVDS clock).

User manual say: "The 20 global clock pins on Virtex-5 devices can be connected to 20 differential or 20 singleended board clocks" page20-21 and "Each clock input can be either single-ended or differential" page 20. That means only either single ended either differential clock is allowed?

The second question is about differential clocks routed to XY GTP transcievers. Can those be used safely as GCLK or RCLK for the GTP opposite banks (banks far away from the GTPs) or an outer clock must be routed on PCB?

thx, Vasile

Reply to
vasile
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You are misinterpreting the documentation. A clock circuit is made up of multiple resources including an package input pin (IBUF or IBUFDS), an optional DCM or PLL and a global clock tree (BUFG).

The paragraph that you quoted was discussing that the package input pin could be either single ended (LVCMOS, SSTL, HSTL, etc) or differential (LVDS). These package pins would be connected to a physical on board clock device that outputs a specific signaling standard. A

The MGTREFCLK input pins are intended only for use with the RocketIO transceivers. These can be driven into the array, but it must be done through an instantiated RocketIO and the only allowed connection from here is to a BUFG. It is not recommended to use these pins for anything other than RocketIO based designs. In particular you would not want to use these pins for system synchronous designs as the timing is not the same as defined clock input pins.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

OK, thank you, this is answering just to a part of my question. Can I route both differential and single ended clocks to the same GCLK dedicated bank (like bank3 in LX330T ) and use both of them (one is LVDS as you say and the other is single ended 2.5V clock) ? Where can I found this info in the datasheet please, so I will not misinterpreting anymore ?

thnak you, Vasile

Reply to
vasile

The clock input pins are independently configurable just like the other IOs, so yes you can have both single ended and differential inputs in bank 3. The limitations on what IO standards can be used at the same time in this bank is the same as for all other banks.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Thank you, Ed.

Vasile

Reply to
vasile

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