Hi to everybody,
I'ts not very clear from the Virtex 5 User guide, Clock resources chapter if it's possible to route (on different GCLK inputs) single ended and differential CLKs. Then at configuration time use either the single ended clock (routed at the P side of the differential input pair) or differential clock (say LVDS clock).
User manual say: "The 20 global clock pins on Virtex-5 devices can be connected to 20 differential or 20 singleended board clocks" page20-21 and "Each clock input can be either single-ended or differential" page 20. That means only either single ended either differential clock is allowed?
The second question is about differential clocks routed to XY GTP transcievers. Can those be used safely as GCLK or RCLK for the GTP opposite banks (banks far away from the GTPs) or an outer clock must be routed on PCB?
thx, Vasile