Field-Programmable Gate Arrays

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Automotive Electronic Control

Hi, I'm looking for a control unit (plc, control card, control module) for construction equipment (excavator). It shoul...
4 comments posted 19yrs
posted by icegray
4 comments posted 19yrs posted by icegray

partial reconfiguration, par error

When I implement the reconfigure module, after ngdbuild, map and continue with par there show some error but look like...
1 comments posted 19yrs
posted by gilbert1219com
1 comments posted 19yrs posted by gilbert1219com

BRAM bytewide write enable problem

I have created two BRAM using coregen (BLK_MEM_GEN_V2_4) , out of them #1 is not supporting byte enable #2 supports byt...
0 comments posted 19yrs
posted by ecbharat
0 comments posted 19yrs posted by ecbharat

Xilinx GTP based serial link

Hi everyone, I am investigating about the best communication link protocol for my high throughput data link. I am requi...
0 comments posted 19yrs
posted by jayasanka.piyaratna
0 comments posted 19yrs posted by jayasanka.piyaratna

FREE BACKGROUND CHECK

Why pay for an expensive background check when you can conduct your own for absolutely free. Check it out at Check it ou...
0 comments posted 19yrs
posted by skebw2rozehshrghlhmd66y6
0 comments posted 19yrs posted by skebw2rozehshrghlhmd66y6

CRC calculation of Virtex 4 bitstream

hi. i have to calculate the crc checksums of a virtex 4 bitstream. there are two ckecksums: one direct after the config...
2 comments posted 19yrs
posted by lembke.stefan
2 comments posted 19yrs posted by lembke.stefan

Does Modelsim work under Windows Vista?

Xilinx's ISE 9.2 now supports Windows Vista (32-bit only.) Do other tools like (Mentor Modelsim and Xilinx XPS/EDK) run...
3 comments posted 19yrs
posted by helpme
3 comments posted 19yrs posted by helpme

Xilinx Microblaze EDK and Virtex5/LXT TEMAC core?

I've looked through Xilinx's website, but I can't determine whether the embedded 10/100/1000 gigabit MAC is supported i...
0 comments posted 19yrs
posted by helpme
0 comments posted 19yrs posted by helpme

DDR RAM timing contraints

hei list, i am working on a DDR-Ram controller for the ml401 board from xilinx. the controller i am using is generated...
0 comments posted 19yrs
posted by paul
0 comments posted 19yrs posted by paul

Configuring Impact on any version of linux

Hi guys i want to use Xilinx 8.2i or 9.1i or even 7.1i for burning codes on my FPGA board using the Parallel port on Li...
2 comments posted 19yrs
posted by ankitanand1986
2 comments posted 19yrs posted by ankitanand1986

Enterpoint Web Site

For those of you frustrated with our PayPal payments system we have hopefully now got it sorted. Any more problems plea...
0 comments posted 19yrs
posted by removethisthenleavejea
0 comments posted 19yrs posted by removethisthenleavejea