Field-Programmable Gate Arrays

[ANN] FPGAOptim - Do you know where your slices are going...?

Hi all, I now have the opportunity to make available to the wider world an internal tool I developed to focus my area-o...

6 comments posted 18yrs

posted by martin.j.thompson

6 comments posted 18yrs posted by martin.j.thompson

BRAM bytewide write enable problem

I have created two BRAM using coregen (BLK_MEM_GEN_V2_4) , out of them #1 is not supporting byte enable #2 supports byt...

0 comments posted 18yrs

posted by ecbharat

0 comments posted 18yrs posted by ecbharat

ANNOUNCE: Embedded hw/sw developer freebies by Nikolaos Kavvadias

Hello fellow developers, users and friends This is a list of free (some of them GPL'ed) tools that I have written over...

0 comments posted 18yrs

posted by nkavv

0 comments posted 18yrs posted by nkavv

Xilinx GTP based serial link

Hi everyone, I am investigating about the best communication link protocol for my high throughput data link. I am requi...

0 comments posted 18yrs

posted by jayasanka.piyaratna

0 comments posted 18yrs posted by jayasanka.piyaratna

Any advice on Steve Kilts' "Advanced FPGA Design: Architecture, Implementation, and Optimization" ?

Greetings, Have any of you read Steve Kilts' book "Advanced FPGA Design: Architecture, Implementation, and Optimization...

0 comments posted 18yrs

posted by james

0 comments posted 18yrs posted by james

FREE BACKGROUND CHECK

Why pay for an expensive background check when you can conduct your own for absolutely free. Check it out at Check it ou...

0 comments posted 18yrs

posted by skebw2rozehshrghlhmd66y6

0 comments posted 18yrs posted by skebw2rozehshrghlhmd66y6

CRC calculation of Virtex 4 bitstream

hi. i have to calculate the crc checksums of a virtex 4 bitstream. there are two ckecksums: one direct after the config...

2 comments posted 18yrs

posted by lembke.stefan

2 comments posted 18yrs posted by lembke.stefan

Does Modelsim work under Windows Vista?

Xilinx's ISE 9.2 now supports Windows Vista (32-bit only.) Do other tools like (Mentor Modelsim and Xilinx XPS/EDK) run...

3 comments posted 18yrs

posted by helpme

3 comments posted 18yrs posted by helpme

Xilinx Microblaze EDK and Virtex5/LXT TEMAC core?

I've looked through Xilinx's website, but I can't determine whether the embedded 10/100/1000 gigabit MAC is supported i...

0 comments posted 18yrs

posted by helpme

0 comments posted 18yrs posted by helpme

Answer: maximum number of state machines in a current chip: > 500k

Hi, Here is the answer to the maximum number of state machines in a current chip: > 500k. My original answer posing has...

6 comments posted 18yrs

posted by wtxwtx

6 comments posted 18yrs posted by wtxwtx

DDR RAM timing contraints

hei list, i am working on a DDR-Ram controller for the ml401 board from xilinx. the controller i am using is generated...

0 comments posted 18yrs

posted by paul

0 comments posted 18yrs posted by paul

Configuring Impact on any version of linux

Hi guys i want to use Xilinx 8.2i or 9.1i or even 7.1i for burning codes on my FPGA board using the Parallel port on Li...

2 comments posted 18yrs

posted by ankitanand1986

2 comments posted 18yrs posted by ankitanand1986

Enterpoint Web Site

For those of you frustrated with our PayPal payments system we have hopefully now got it sorted. Any more problems plea...

0 comments posted 18yrs

posted by removethisthenleavejea

0 comments posted 18yrs posted by removethisthenleavejea

Using PlanAhead for Partial Reconfiguration

I have a doc. named "Partial Reconfiguration Design with PlanAhead 9.2" and use PR_V5_DVI.zip for example. While follow...

1 comments posted 18yrs

posted by gilbert1219com

1 comments posted 18yrs posted by gilbert1219com

how interfacing of cpld and cpu done?

please give me information about inerfacing of cpld xc9572 & cpu

1 comments posted 18yrs

posted by nanaware_amit

1 comments posted 18yrs posted by nanaware_amit