Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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USR_ACCESS_VIRTEX4 usage
Hello all, I would like to use the USR_ACCESS_VIRTEX4 primitive to access an additional bitstream stored in a config flash. The situation is following: * I have a master FPGA (Virtex-4FX) and a slave...
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16 years ago
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Xilinx ISE Timing Report Question
Hi, I have a question about Xilinx post-P&R static timing reports. I understand most of the constraints listed in the timing report, but some of them don't appear in my UCF and have me a bit confused....
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16 years ago
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Xilinx Virtex-II Newbie
Hello, I am in some way a newbie in getting things to run on an FGPA, so I would be helpful if someone could help me a little bit out how to get started. I have implemented a simple processor...
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16 years ago
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FPGA for hobby use
A few month ago I asked for a recommendation for FPGA (not a ready to use demo board) which could be handled with simple home equipment. I got the link to: We ordered a few samples and did some...
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16 years ago
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Xilinx Encrypted bit file
I know Xilinx keeps its bit file header format secret. But, does anyone know how to detect if a bit file is encrypted or not? As part of our manufacturing builds, we need to make sure the bit file we...
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16 years ago
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grouping bits to form bus in VCD file
Hi I just have another issue. I try comparing the VCD files generated by Modelsim to a reference VCD file. Unfortuantely this is not working, because the modelsim represents a 32-bit signal as 32...
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16 years ago
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VCD Files Viewer?
Hello I just generated with modelsim a VCD file and I wonder if it is possible to view this VCD file with modelsim? I tried to open it but I got the error message: # WLF Error: File is not a WLF file:...
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16 years ago
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REFCLK signal in Hard TEMAC core
I am troubleshooting a tri-mode ethernet interface utilizing the hard MAC core provided in the VirtexFX series of FPGAs. I've instantiated the hard TEMAC wrapper and the plb_TEMAC core that connects...
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16 years ago
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Synthesis-place&route performance test.
I would like to find out how well different system setups performs when it comes to Synthesis, Place & Route with Xilinx ISE tools. I would like you to synth/place/route the source package below. And...
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16 years ago
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Chipscope Server for PowerPC?
Hi All, I have got 2 Virtex5, each with its own PlatformFlash chained together for Programming/Debugging over JTAG. In-System-Programming is easy, because of the availability of the...
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16 years ago
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[EDK simulation] synopsys translate_off
Dear I would like to ask some help, for simulating EDK project. I did following steps: -------------------------------------------------------------------------------- 1. Generate "simulation model...
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16 years ago
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how to make ports visible?
Hello all, I am trying to make the PORT B of a BRAM visible in EDK ver.6.2i . The only ports can make visible from PORT B is only the CLK. have you any idea how to do the rest ports of BRAM PORT B...
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16 years ago
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Structured way of changing eg time constants for real world build / simulation?
Frequently when doing simulation of a design I'll change time constants so I can run the simulation in a reasonable timescale. I like to keep things simple so to date this has mostly involved...
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16 years ago
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implementing MAC protocols on fpga
hi fnds, i am working on implementing MAC protocols on fpga...i am a bit stuck in the way to start the process, like, how to give 2 simultaneous inputs to an fpga? and how to detect if collision has...
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16 years ago
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bidirectional in fpga
Hi , Is it possible to implement signal declared as bidirectional (i.e.,inout) in example i have to declare bidirectional data bus D[7:0].should i use as two separate unidirectional? regards, fazal
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16 years ago
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