Field-Programmable Gate Arrays

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USR_ACCESS_VIRTEX4 usage

Hello all, I would like to use the USR_ACCESS_VIRTEX4 primitive to access an additional bitstream stored in a config fl...
2 comments posted 18yrs
posted by no
2 comments posted 18yrs posted by no

Xilinx ISE Timing Report Question

Hi, I have a question about Xilinx post-P&R static timing reports. I understand most of the constraints listed in the t...
2 comments posted 18yrs
posted by ftpeter
2 comments posted 18yrs posted by ftpeter

Xilinx Virtex-II Newbie

Hello, I am in some way a newbie in getting things to run on an FGPA, so I would be helpful if someone could help me a...
23 comments posted 18yrs
posted by Andrew.G
23 comments posted 18yrs posted by Andrew.G

FPGA for hobby use

A few month ago I asked for a recommendation for FPGA (not a ready to use demo board) which could be handled with simpl...
34 comments posted 18yrs
posted by klee
34 comments posted 18yrs posted by klee

Xilinx Encrypted bit file

I know Xilinx keeps its bit file header format secret. But, does anyone know how to detect if a bit file is encrypted o...
6 comments posted 18yrs
posted by akhailtash
6 comments posted 18yrs posted by akhailtash

grouping bits to form bus in VCD file

Hi I just have another issue. I try comparing the VCD files generated by Modelsim to a reference VCD file. Unfortuantel...
0 comments posted 18yrs
posted by Heinrich255
0 comments posted 18yrs posted by Heinrich255

VCD Files Viewer?

Hello I just generated with modelsim a VCD file and I wonder if it is possible to view this VCD file with modelsim? I t...
3 comments posted 18yrs
posted by Heinrich255
3 comments posted 18yrs posted by Heinrich255

REFCLK signal in Hard TEMAC core

I am troubleshooting a tri-mode ethernet interface utilizing the hard MAC core provided in the VirtexFX series of FPGAs...
0 comments posted 18yrs
posted by JimboD2
0 comments posted 18yrs posted by JimboD2

Synthesis-place&route performance test.

I would like to find out how well different system setups performs when it comes to Synthesis, Place & Route with Xilin...
2 comments posted 18yrs
posted by posedge52
2 comments posted 18yrs posted by posedge52

Chipscope Server for PowerPC?

Hi All, I have got 2 Virtex5, each with its own PlatformFlash chained together for Programming/Debugging over JTAG. In-...
0 comments posted 18yrs
posted by biker
0 comments posted 18yrs posted by biker

[EDK simulation] synopsys translate_off

Dear I would like to ask some help, for simulating EDK project. I did following steps: --------------------------------...
8 comments posted 18yrs
posted by pasacco
8 comments posted 18yrs posted by pasacco

how to make ports visible?

Hello all, I am trying to make the PORT B of a BRAM visible in EDK ver.6.2i . The only ports can make visible from PORT...
1 comments posted 18yrs
posted by lastval
1 comments posted 18yrs posted by lastval

implementing MAC protocols on fpga

hi fnds, i am working on implementing MAC protocols on fpga...i am a bit stuck in the way to start the process, like, h...
3 comments posted 18yrs
posted by dilip.manu
3 comments posted 18yrs posted by dilip.manu

bidirectional in fpga

Hi , Is it possible to implement signal declared as bidirectional (i.e.,inout) in FPGA.For example i have to declare bi...
5 comments posted 18yrs
posted by fazulu.vlsi
5 comments posted 18yrs posted by fazulu.vlsi