Latest threads in Field-Programmable Gate Arraysshow only best voted threads
| Subject | Author | Posted | Replies | |
|---|---|---|---|---|
|
|
Asynchronous FIFO Latency.
Hi, I recently read that asynchronous FIFOs have certain clock latency. Can somebody please explain a bit about why is there a latency, or delay, before the data can be read from an asynchronous FIFO?...
1
|
16 years ago
|
1 | |
|
|
ANNC: Display System Embedded Design with FPGA Webcast
Lattice is holding a webcast this Thursday, November 15th, "Display System Embedded Design with Instant-On FPGAs." The presenter will be Kerry Howell, from our solutions marketing group. This webcast...
—
|
16 years ago
|
— | |
|
|
DDR in spartan 3E
Hi, I use the Spartan display board (spartan 3E 1600), and I try to save a complete video frame (1280*1024) in a DDR. But I have many problem to simulate my code with the controler (from Mig 1.72,...
—
|
16 years ago
|
— | |
|
|
Students: where to go for help
Students, Please ask your professor to file a XUP webcase for you, if he/she agrees that yours is a problem that requires our help. It is impossible for Xilinx to support all students directly, so our...
4
|
16 years ago
|
4 | |
|
|
Spartan3E Slave Serial Daisy chain
Hi All, I've got three Spartan3Es daisy chained together in slave serial mode. I'm attempting to configure the 3 devices from an Atmel AVR reading the configuration from an SDCard. The DONE line is...
7
|
16 years ago
|
7 | |
|
|
Strange VHDL Error
Hi I have a simple package that looks as follows: library IEEE; use use package RISC_Pkg is -- Clock type subtype T_clk is std_logic; -- Reset type subtype T_rst is std_logic; subtype T_PIPE_REG_CTRL...
5
|
16 years ago
|
5 | |
|
|
EDK 8.2 tool : simulator set up
Dear I need to simulate my EDK (8.2) project. Simulator is Modelsim SE 6.1c. I did following steps: ------------------------------------------- In order to compile COMPXLIB, I used the EDK simulation...
2
|
16 years ago
|
2 | |
|
|
[EDK tool] simulation setup
Dear I need to simulate my EDK (8.2) project. Simulator is Modelsim SE 6.1c. I did following steps: ------------------------------------------- In order to compile COMPXLIB, I used the EDK simulation...
1
|
16 years ago
|
1 | |
|
|
Programming connection
Looking for ideas to eliminate the programming connector and replace it with pads/contacts on the board. This is both for cost and size reduction as well as simplifying programming during...
8
|
16 years ago
|
8 | |
|
|
Xilinx USB cable in Fedora 7
I was wondering about peoples success/failure getting the USB cable working in Fedora 7? I am running 64 bit F7 but am running 32 bit ISE. I am trying to use Michael's driver. USB cable is the DLC9G....
1
|
16 years ago
|
1 | |
|
|
Re: Embedded Linux & Code Security
Specifically Altera Statrix-II FPGAs have AES 128 decryption and OTP (fuse) non-readable key storage for the configuration bitstream. So: run Linux on a NIOS soft core in one of these FPGAs. Encrypt...
1
|
16 years ago
|
1 | |
|
|
newbie to 16v8
Hello group, I'm new to this field and currently learning how 16v8 architecture is designed. Of course, pretty confused but as my first experiement I need to implement a logical function and also...
19
|
16 years ago
|
19 | |
|
|
Is "Insight IJC-02" and "Xilinx parallel download cable" the same?
When looking at this schematic: And comparing with the pcb layout of Insight jtag IJC-02 parallel port dongle. They seem to be the same thing. Is that so .. ? Any catches with it?, I saw some posts...
—
|
16 years ago
|
— | |
|
|
SystemACE generation
Hi, I am ajith again. Sorry I forgot to tell you about the error message. The error that I am getting is "Unable to open ELF file, ELF file might have corrupted." ajith.
—
|
16 years ago
|
— | |
|
|
System ACE generation
Hi, I am trying to generate system ACE file in EDK 9.1 . I am trying to combine bitstream with zImage.elf which is used to boot Monta vist linux in XUP board. I am using the following command to...
—
|
16 years ago
|
— |