Field-Programmable Gate Arrays

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FPGA Editor (9.2.03i) under Linux x86_64

I am not able to run the fpga_editor (64-bit ISE install) under my Fedora 7, x86_64 system. After I set the DISPLAY var...
8 comments posted 18yrs
posted by no
8 comments posted 18yrs posted by no

Why doesnt XST RAM for this VHDL description

Hi, I am using a Xilinx Virtex2 Board and would like to have an instruction and data RAM. I was following the guideline...
3 comments posted 18yrs
posted by Patrick.Bateman23
3 comments posted 18yrs posted by Patrick.Bateman23

Virtex5 Evaluation Board

Hi We are thinking of buying a Xilinx Virtex5 evaluation board. At the moment this one seems to be our favorite: http:/...
4 comments posted 18yrs
posted by Patrick.Bateman23
4 comments posted 18yrs posted by Patrick.Bateman23

EDK 9.2 and virtex 2 devices

Hi all, i'm currently trying to make an virtex2 project with edk 9.2i. Unfortunately all virtex2 based boards are remov...
12 comments posted 18yrs
posted by wassatsch
12 comments posted 18yrs posted by wassatsch

33+ Regs in PLB IPIF

I have created a custom peripheral in EDK 9.1/ISE 9.1 that needs to have 100 registers and communicates with the PowerP...
4 comments posted 18yrs
posted by mdhicks2
4 comments posted 18yrs posted by mdhicks2

Parallel to Serial ASI ...

Hi, I have two simple questions : - To implement a conversion Paralle to Serial ASI (paralel data TS from Digital Tuner...
2 comments posted 18yrs
posted by 78kappa78(at)virgilio(dot)it
2 comments posted 18yrs posted by 78kappa78(at)virgilio(dot)it

TPS75003 Spartan-3(E) Regulator Design

Dear All, The TPS75003 is a triple voltage regulator designed for the Spartan-3 & Spartan-3E series. It's got some quit...
5 comments posted 18yrs
posted by ajg112
5 comments posted 18yrs posted by ajg112

Microblaze books

hello all, I am looking for some books for microblaze and some examples with assembly for microblaze. since now i havent...
3 comments posted 18yrs
posted by lastval
3 comments posted 18yrs posted by lastval

Update to Xilinx ISE 9.2

Hi Sorry, for putting this question here but I have heard that the Xilinx support is quite busy so perhaps someone can...
5 comments posted 18yrs
posted by Harald
5 comments posted 18yrs posted by Harald

mb-g++ linker script problem 8.2i

Specification EDK version:8.2i FPGA Board: Virtex II Pro I've tried generating a linker script to map the input object...
1 comments posted 18yrs
posted by priyanthads
1 comments posted 18yrs posted by priyanthads

GTKWave 3.1.1 for win32

Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.1.1 which supports reload now. http://www.dspia.com...
3 comments posted 18yrs
posted by kal*
3 comments posted 18yrs posted by kal*