Field-Programmable Gate Arrays

Why doesnt XST RAM for this VHDL description

Hi, I am using a Xilinx Virtex2 Board and would like to have an instruction and data RAM. I was following the guideline...

3 comments posted 18yrs

posted by Patrick.Bateman23

3 comments posted 18yrs posted by Patrick.Bateman23

Xilinx Virtex 5 ISERDES vs ISERDES_NODELAY: which is better for DDR?

The Virtex 5 Library has two design elements for the ISERDES. The ISERDES_NODELAY obviously does not include the delay...

0 comments posted 18yrs

posted by barry374

0 comments posted 18yrs posted by barry374

Virtex5 Evaluation Board

Hi We are thinking of buying a Xilinx Virtex5 evaluation board. At the moment this one seems to be our favorite: http:/...

4 comments posted 18yrs

posted by Patrick.Bateman23

4 comments posted 18yrs posted by Patrick.Bateman23

EDK 9.2 and virtex 2 devices

Hi all, i'm currently trying to make an virtex2 project with edk 9.2i. Unfortunately all virtex2 based boards are remov...

12 comments posted 18yrs

posted by wassatsch

12 comments posted 18yrs posted by wassatsch

problem with adding custom logic to an IP core (xilinx edk)

Hi all, I'm experiencing problems with adding custom logic to an IP core that I have generate in EDK. I changed the vhd...

3 comments posted 18yrs

posted by giuliopulina

3 comments posted 18yrs posted by giuliopulina

33+ Regs in PLB IPIF

I have created a custom peripheral in EDK 9.1/ISE 9.1 that needs to have 100 registers and communicates with the PowerP...

4 comments posted 18yrs

posted by mdhicks2

4 comments posted 18yrs posted by mdhicks2

Parallel to Serial ASI ...

Hi, I have two simple questions : - To implement a conversion Paralle to Serial ASI (paralel data TS from Digital Tuner...

2 comments posted 18yrs

posted by 78kappa78(at)virgilio(dot)it

2 comments posted 18yrs posted by 78kappa78(at)virgilio(dot)it

TPS75003 Spartan-3(E) Regulator Design

Dear All, The TPS75003 is a triple voltage regulator designed for the Spartan-3 & Spartan-3E series. It's got some quit...

5 comments posted 18yrs

posted by ajg112

5 comments posted 18yrs posted by ajg112

Microblaze books

hello all, I am looking for some books for microblaze and some examples with assembly for microblaze. since now i havent...

3 comments posted 18yrs

posted by lastval

3 comments posted 18yrs posted by lastval

Update to Xilinx ISE 9.2

Hi Sorry, for putting this question here but I have heard that the Xilinx support is quite busy so perhaps someone can...

5 comments posted 18yrs

posted by Harald

5 comments posted 18yrs posted by Harald

mb-g++ linker script problem 8.2i

Specification EDK version:8.2i FPGA Board: Virtex II Pro I've tried generating a linker script to map the input object...

1 comments posted 18yrs

posted by priyanthads

1 comments posted 18yrs posted by priyanthads

GTKWave 3.1.1 for win32

Hi, I updated the GTKWave for Win32 port I am maintaining. It's at 3.1.1 which supports reload now. http://www.dspia.com...

3 comments posted 18yrs

posted by kal*

3 comments posted 18yrs posted by kal*

Xilinx WebPack 9.2i: Download not possible, wrong links

Hello, because download was not possible I checked after some tries (as always hecticness) the links - the links are no...

0 comments posted 18yrs

posted by WeikEngOff

0 comments posted 18yrs posted by WeikEngOff

synthesizing vqm with parameters with quartus 7.1sp1

Hi, I have a verilog module in my project, which is instantiated in the design 3 times, each time with different parame...

1 comments posted 18yrs

posted by hershkoy

1 comments posted 18yrs posted by hershkoy

Altera webpack for Linux?

I noticed that the Xilinx webpack version of ISE now runs in Linux. I seem to recall in the past that the webpack was a...

3 comments posted 18yrs

posted by jshamlet

3 comments posted 18yrs posted by jshamlet