Xilinx ISE Timing Report Question

Hi,

I have a question about Xilinx post-P&R static timing reports. I understand most of the constraints listed in the timing report, but some of them don't appear in my UCF and have me a bit confused.

Could anyone tell me what the time groups J_CLK and U_CLK are and why they are configured this way? I can't find any mention of these in the documentation. I've attached a bit of my .twr to the bottom of the post. I've seen them in several project so my guess is that they have something to do with using chipscope or that these are the names of some sort of global clock net.

Thanks in advance, Peter

-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Level

-------------------------------------------------------------------------------- TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" | 30.000ns | 11.588ns | 2 TO TIMEGRP "J_CLK" 30 ns | | |

-------------------------------------------------------------------------------- TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | 15.000ns | 4.473ns | 1 TO TIMEGRP "J_CLK" 15 ns | | |

-------------------------------------------------------------------------------- TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | 15.000ns | 1.496ns | 0 TO TIMEGRP "U_CLK" 15 ns | | |

-------------------------------------------------------------------------------- PATH "TS_U_TO_D_path" TIG | N/A | N/A | N/A

-------------------------------------------------------------------------------- PATH "TS_J_TO_D_path" TIG | N/A | 6.921ns | 32

-------------------------------------------------------------------------------- PATH "TS_D_TO_J_path" TIG | N/A | 5.117ns | 5

--------------------------------------------------------------------------------

Reply to
Peter Klemperer
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On 14 Nov., 18:23, Peter Klemperer wrote: Hi Peter,

using chipscope, you should see an edif-netlist like "icon.edn" or something like this, that will integrated automatically within your toplevel design running ngdbuild. I guess, you'll find a file called "icon.ncf" within the same directory

If you have a look at it's content with a simple editor, you should find said timing-constraints - and they will be automatically linked to your design, too.

They are needed to guarantee chipscope's functionality (JTAG- clock,...)

hope, it helps, Jochen

Reply to
Jochen

Thanks Jochen, that did it for me. I should have grep'd for it.

--Peter

Reply to
Peter Klemperer

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