Xilinx Virtex-II Newbie

I am just reading the XST userguide. There it says that with version

8.1i it is possible to directly specify data with the RAM module or load it from an external source. IN addition it says the multiple write ports in the RAM are supported from version 8.1 on. UNfortuantely I just have version 7.1 and I should have a RAM that has 4 read ports and 2 write ports? Is that somehow to realise with ISE 7.1 or do I need to upgrade to version 8.1?

Many thanks, Andrew

Mixed something up, my Register File should have 4 read ports and two write ports :)

What you are asking for is outside the abilities of the Virtex-II FPGA. Since the FPGA only contains dual-ported memories (either SelectRAM-based or BlockRAM-based), there is no possible way to map such a HDL description to the FPGA device.

You'll have to figure out a mechanism to multiplex the read/write ports such that you have less than or equal to two ports (be they read, write, or read/write ports).

Good luck - welcome to the world of FPGA engineering.

- Nathan

Are you sure that you need 4 read and 2 write ports? Do you need to assign the data read at the time - at the same clock edge? In that case you could just assign the same data read to multiple signals.

How big is your register file? You may create an vhdl component that includes an array of registers (check how to create arrays of signals it is pretty straightforward). With a process inside this component you can assign values to this array where the index of the array represents the location of the register in the register file (address input of the component). You can create another process for reading that can use same or different clock (of different phase) for reading of this array using the input address as an index again.

Within this component you can also manually specified the initial values of those registers.

This way you can also create an instruction memory that contains some array of instructions - these instructions you would also need to specify manually within the vhdl code.

Chipscope with Jtag interface you can use to probe any signals within the FPGA when it is configured. This way you can also read the register file or memory that you created in VHDL.

Hope that this helps, Dan

I know of no tools or FPGAs that currently support inference or instantiation of 4-ported memory.

Sorry.

However, to be slightly more helpful, you still can "fake it." Xilinx suggests such a mechanism here:

Again, it comes down to creatively multiplexing ports.

- Nathan

On Nov 14, 2:49 pm, Andrew Ganger wrote: Virtex-2 or any other Virtex FPGA can implement a RAM with any desired number of ports, if you are willing to time-share operation and multiplex addresses and data. So it is just a trade-off. The BlockRAMs in all Virtex devices have two independent ports, so you can perform two independent accesses simultaneously (two writes, two reads, or a mixture of write and read). Further ports can be created by time-sharing and multiplexing, which of course costs chip area and increases access time. But those are the usual trade-offs that smart engineers are asked to evaluate and implement every day. What else is new? Peter Alfke, Xilinx

Yes, I have defined an own ISA. There are instructions that take up to

4 src operands and can write up to two results back to the register file. So I need these 4 read ports for some, not all, instructions!

Two write ports sounds dangerous :) - but classic RISC devices might need 3 read ports, and one write port

Rd = Ra OPERAND Rb OPERAND Rc

one fast/simple idea I had for emulating this on dualport memory is to use two blocks and simply parallel the one write port

- so the two have identical info, and would actually give 4 read ports

Yes, it's a little redundant, but easy to implement, and the RegFiles are small anyway.

-jg

Are you implementing MIPS32? Do you have instructions that have two register operands?

My question should be: do you have instructions that use 4 register operands?

So that's 24 bits of operand, leaves 8 bits of opcode, if 32 bit ?

Which opcodes need to write two results, in one cycle ?

I can think of MUL, DIV, MOD that might write two results, (but not so much in one cycle) but the only other instances I could think of would be extended size opcodes (normally handled reg-paired), and maybe merge of a MOV.

Source code does not tend to have two writes per expression ?

-jg

You have several options besides time multiplexing the existing RAM:

- Implement the RAM using flops instead of RAM. This may be reasonable if you do not have too many registers. I'm not sure if xst will infer the flops, but I would try something like this:

reg [31:0] r[15:0]; // 512 flops, not ram.

always @(posedge clk) begin if (write_enable_a) r[write_addr_a]

Register file should be no problem, inplemented in the FPGA fabric; though it could be fairly large (assuming your description is synthesisable). I suspect Nathan was talking about multi-port larger blocks of memory.

Even there you can do it; multiplexing is simplest if your performance needs are low, but it's not the only way. For example, to increase the number of read ports, you can simply parallel memories, writing to them all simultaneously. If you can get away with 2:1 multiplexing the write ports, that may be all you need.

Do you need full bandwidth on all six ports simultaneously?

In any case, use the component you have as a wrapper for the detailed implementation for that behaviour.

- Brian

Yeah, multiplication is one example that uses two write ports. The ISA is tailored towards a very specific domain of applications, so therefore I have some not straight forward instructions. But it would be handy in this case to have instructions that take 4 inputs and generate 2 outputs.

Yeah, it might be dangerous, but in my case I would need two write ports ;).

So yeah, this sounds like a good idea. So I would have two RAM blocks each with two read, and two write ports. In this case I write the result back simultanlously in both register files. Looks like a good idea for a first evaluation!

Thanks!

Thanks for your comment Brian. I will try and see what the tool tells me when trying to synthesise it. Is there an upper limit for read and write ports for such kind of register files? Or is this just the case for memories?

Yeah that also sounds like a good idea. But as memory I have a simple single port read/write interface!

Cheers!

Probelem with this is what if more than two registers that need to be written are located at the same RAM block! I am using 8 parallel blocks in my design as I am writting 8 memory locations at a time but I am sure that all 8 memory locations belong to different RAM block.

Sorry, I dont understand that. You suggest also to use 2 RAM block with each two read ports. They both should contain the same register values, so in other words, each RAM block requires 2 write ports so that I can keep the values in both registers consistent!