Hi
I just have another issue. I try comparing the VCD files generated by Modelsim to a reference VCD file. Unfortuantely this is not working, because the modelsim represents a 32-bit signal as 32 single bits whereas the reference VCD file treats the whole 32 bits as a bus.
So is there a way to group single bits in VCD to a single Bus?
Modelsim VCD has single bits
pipe.arc_fe_dc.fe_dc[31] Q+ from regr.vcd pipe.arc_fe_dc.fe_dc[30] R+ from regr.vcd .... pipe.arc_fe_dc.fe_dc[1] o+ from regr.vcd pipe.arc_fe_dc.fe_dc[0] p+ from regr.vcd
Reference VCD looking for a bus of 32 bits and outputs error: NO match pipe.arc_fe_dc.fe_dc[31:0]
Thanks, Heinrich