I am troubleshooting a tri-mode ethernet interface utilizing the hard MAC core provided in the VirtexFX series of FPGAs. I've instantiated the hard TEMAC wrapper and the plb_TEMAC core that connects the plb bus to the hard core. I'm still trying to read/write to the PHY's registers over the management interface. I'm using GMII between the MAC and PHY.
The hard temac wrapper core has a REFCLK input signal. The only mention of this in the datasheet is regarding SGMII mode. REFCLK is used for calibrating the IDELAYCTRL blocks needed for SGMII. I assumed that for GMII, this clock was not needed. However, looking at the plb_temac datasheet, they list an mhs file example for a dual MAC GMII ethernet interface. In this example, they show REFCLK connected to the plb clock.
Does anyone know if this signal is needed? Currently when I attempt a PHY register read, I see both Management interrupts asset but never see any data back. I have also not seen any activity on the MDIO/MDC lines, so im led to believe this is a problem with how my cores are configured.
Thanks