Structured way of changing eg time constants for real world build / simulation?

This isn't a real solution, but sometimes hacks are good enough.

grep -r XXXX .

That will find them all. As long as there aren't many you can check them by eye.

Aye Hal, I have windows Grep on my PC so can create a tool in Textpad to do this and capture the results fairly easily.

The problem is that I keep forgetting to check.

:-(

Nial.

constant ddr_reset_time : integer := 200 us / clk_period; -- cycles constant sim_reset_time : integer := 2 us / clk_period; -- cycles

function reset_time return integer is variable temp:integer := ddr_reset_time; begin

-- pragma synthesis off temp := sim_reset_time;

-- pragma synthesis on return temp end;

...

reset_counter

Nice trick Brian; I'll have to remember that...

I would use a generic, passed up to the top level, with a default value defined for synthesis. Then when you instantiate the top level module in your testbench for simulation, override the default value with a generic map. This can be done for one or a whole group of generics. If you use a group of generics, you can define them as elements of a record type in a package, and every entity takes that generic record. That way when you want to add a generic for some lower level entity, you just have to add it's element to the record definition, then set it at the top (default and testbench), and use it at the leaf level where needed. The record definition acts like a conduit through which you can pass anything you want.

Andy

Another nice trick, although after spending ages trying to get my head round a design I had to pick that used records on port maps everywhere I tend to try to avoid them.

Sometimes they can be a great tool for obfuscation :-)

Nial.

Personally I use two copies of a VHDL package with constants etc in there. Named clearly as SIM or SYNTHESIS. You just need to carefully keep the two copies in track with any extra values added.

John Adair Enterpoint Ltd. - Home of Darnaw1 the PGA FPGA Module.

Yeah, records on ports can get really ugly, especially since everything ends up being of mode inout, with default 'Z' drivers, etc.

Fortunately for generics, which are "in" only, it is not as bad.

I've been wishing for user defined modes for record type ports (or procedure arguments), used in lieu of in, out or inout, that would allow you to specify the mode of each individual element. If only we could do something like:

type bus_type is record data : std_logic_vector(31 downto 0); ack : std_logic; ... end record; mode slave of bus_type is (data => inout; ack => out; others => in); mode master of bus_type is (data => inout; ack | clk | rst => in; others => out);

Andy

If you aren't too attached to VHDL you could look at SystemVerilog which has exactly this functionality. Keywords to look for are "interface" and "modport".

/Andreas