Hello all,
I would like to use the USR_ACCESS_VIRTEX4 primitive to access an additional bitstream stored in a config flash. The situation is following:
- I have a master FPGA (Virtex-4FX) and a slave FPGA (Spartan-3A). The slave FPGA is located on an additional board and it is NOT daisy-chained with the master one.
- Master FPGA gets configured out of platform flash in master serial mode.
- I need to configure even the slave FPGA. The only non-volatile source of its configuration data is the platform flash connected to the master FPGA.
I used STARTUP_VIRTEX4 primitive to take control over the CCLK and DONE signals. While generating bitstream I used the "-g DONE_cycle:KEEP" option. From my measurements of the interface between flash and Virtex-4, this part of the design works fine. I fully control the signals, DONE does not go high anywhere in the middle, and flash sends me additional bitstream data.
To access additional bitstream I instantiated the USR_ACCESS_VIRTEX4 primitive, but here is the problem. Even though I see the data on the DIN input of the Virtex-4, the DATAVALID output of the USR_ACCESS_VIRTEX4 primitive never goes high. So that I am unable to reach this data inside the Virtex-4 FPGA.
The Virtex-4 Libraries Guide for HDL Design says: The PROM should contain a packet of data with the USR_ACCESS register as the target. I generated my PROM file using iMPACT simply putting two bitstreams into single MCS file what is probably wrong. I think my MCS should contain normal master FPGA bitstream followed by the slave FPGA bitsream with target set to USR_ACCESS. Is there any way how to set target for the second bitsream in MCS to USR_ACCESS so that I could access it from my master FPGA?
If I am trying to do something impossible, is there another approach how read slave configuration data from platform flash using master FPGA? I cannot do it simply controlling flash pins, as they are not connected to IO pins of the FPGA but to dedicated configuration pins only.
Thanks for advices, Jan