Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Fixed point number hardware implementation
Hai, I want to know which is the right way of implementing and usage of fixed point number data types in hardware(industry standard)..I have referred various FIR implementations where they are mostly...
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15 years ago
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Synthesis results when testing for 'X' and 'U'
Sometimes it can be a bit tricky to stop 'X's and 'U's creeping into the logic, especially at startup initialisation. If any logic tries to use these values then Modelsim cheerfully spawns lots of...
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15 years ago
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Xilinx Webpack
Hi all What are the limitations of the free Xilinx Webpack ? Does any one know ? Thanks EC
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15 years ago
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Altera Cyclone II EP2C20F484C6N
I have 240 extra pieces of the Altera EP2C20F484C6N and we will not be able to use. Parts are new in original factory sealed packaging. Please let me know if you can use. I should be able to supply...
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15 years ago
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Cadence offers to buy Mentor Graphics for $1.45B
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15 years ago
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Basic Questions about MIG (Memory Interface Generator)
Hi I need little help about ISE MIG tool. I have a couple baic questions and if someone can answer me I would be very greatfull. First thing I wanted to ask is: "does MIG gives me oportunity to define...
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15 years ago
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Xilinx Spartan FPGA BlockRAM in Simulation
My desig directly instantiates Xilinx block ram ramb16_s18_s18, in order to verify that those block rams have been integrated correctly in the design, I'm using the block ram verilog file from ISE...
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15 years ago
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Virtex5 FPGA Board and USB interface
Dear all, I am working on a project where I need to store datas on the Flash memory of my FPGA board. I would like to do it with the USB interface but it is much more complicated than I could thought....
5
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15 years ago
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FPGA configuration Beginner questions...
hello as i mentioned earlier, i'm a beginner with fpgas. in fact, this is the first time i'm configuring an fpga.... I am using the XUP Virtex2Pro Development board, device : XCV2P30, with EDK 9.1i I...
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15 years ago
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Base System Builder problem... no board
hello. i use EDK 9.1, and have a XUP Virtex 2 pro development board with me, device: XCV2P30. In Base System Builder, in the boards drop down meni, i donot find this board listed. what do i do?...
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15 years ago
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Rocket IO alignment, clocks
Hi all, We are using Rocket IO on Virtex 2 pro and we are facing some problems. 1- What is the user frequency clock ? TXUSRCLK or TXUSRCLK2 ? We want to use in half mode rate, REFCLK = 75 MHz,...
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15 years ago
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XAUI v7.2 - timing issue - *channel bonding attributes*
I am using a XAUI core in my design for a PCIe board with a Xilinx Virtex - 5 LX110t FPGA. The board specifications require the GTP dual tiles of XAUI to be constrained to locations X0Y0 and X0Y7...
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15 years ago
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TXCOMSTART/TXCMOTYPE of V5 SATA GTP with ISE10.1.1
1>is TXCOMSTART/TXCMOTYPE useful? My SATA controller includes OOB generate/detect circuit.During simulation,The V5 SATA GTP works well even if TXCOMSTART/TXCMOTYPE tied ground.I only input...
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15 years ago
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Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
I've seen messages from regular posters saying that they run Modelsim/XE Starter Edition in Linux. This evidently works for the node-locked 'disk-id' based licenses. But if you have a full license, on...
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15 years ago
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How to define the Dout width of DA FIR logic Core
Hi, I want to use Xilinx DA FIR logic core (Ver 9.0) to generate many FIR blocks. The wordwidth of Dout is defined as the following: DOUT[R-1:0]: FILTER OUTPUT SAMPLE R-bit-wide output sample bus for...
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15 years ago
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