Field-Programmable Gate Arrays

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Linked Group for FPGAs & CPLDs

Hi, There is a new FPGA Linked in Group. Joining will allow you to find and contact other FPGA, CPLD members on LinkedI...
2 comments posted 18yrs
posted by vikashrungta
2 comments posted 18yrs posted by vikashrungta

Xilinx and RAM/ROM monitoring

Hi, I was wondering if a tool exists to monitor the content of a RAM, ROM connected to a Xilinx FPGA. I would like to b...
1 comments posted 18yrs
posted by XSterna
1 comments posted 18yrs posted by XSterna

DC-Fifo with write pointer confirm/clear

Hi, I have designed a VHDL single clock FIFO with write pointer that can either be confirmed or cleared that is the rea...
1 comments posted 18yrs
posted by ALuPin
1 comments posted 18yrs posted by ALuPin

FPGA based database searching

Hello, I've been searching the internet for days now and still I'm not sure about what I am trying to do. Okay now, I'v...
21 comments posted 18yrs
posted by wirdnichtgelesen
21 comments posted 18yrs posted by wirdnichtgelesen

Cellular automata on a S3E SK

Hi group, Another video by me to showcase another application I made. Just to show can be done with a Spartan 3E Starte...
0 comments posted 18yrs
posted by checo22
0 comments posted 18yrs posted by checo22

is lwIP absolutely necessary for tcp-ip?

hello. i am trying to set up ethernet interface between my pc and a XUP Virtex2Pro board, and want to use tcp/ip. xilin...
2 comments posted 18yrs
posted by vikram788
2 comments posted 18yrs posted by vikram788

ANNOUNCE: new version beta0.84 available

Hello All, A new version beta 0.84 is now available. The following changes and additions have occurred. 1. Added eps,pd...
0 comments posted 18yrs
posted by timinganalyzer
0 comments posted 18yrs posted by timinganalyzer

virtex-5: can't use DCM (too low input frequency)

Hi all, I have a camera and a Virtex-5 FPGA, and i would like to store frames in FPGA Block Ram. In my design (that wor...
14 comments posted 18yrs
posted by giuliopulina
14 comments posted 18yrs posted by giuliopulina

Image Sensor Interface.

Hi, I am planning to read an image sensor using an FPGA but I am a little confused about a bunch of things. Hopefully s...
16 comments posted 18yrs
posted by gill81
16 comments posted 18yrs posted by gill81

Newbie Verilog Question / ModelSim

Hi, I am thinking of using Verilog for a project I am working on. Originally I was going to use a processor core (and C...
4 comments posted 18yrs
posted by rl
4 comments posted 18yrs posted by rl

Altera, Cyclone III, PCI, LVCMOS, & 3.3V

Quick summary: Under what circumstances, if any, can you use 3.3V VCCIO for PCI, with Cyclone 3 parts ? I've read Alter...
5 comments posted 18yrs
posted by eteam_remove_me
5 comments posted 18yrs posted by eteam_remove_me

help using lwIP with xilinx EMAC

hello... in order to interface between my pc (via matlab) and the XUP Virtex 2 pro board, i came to know i'll have to u...
2 comments posted 18yrs
posted by vikram788
2 comments posted 18yrs posted by vikram788

virtex 5 security / embedded key memory

Hi , i would like to know which kind of memory that Xilinx use for the encryption key storage ( virtex 5 ) , is it an a...
1 comments posted 18yrs
posted by swissiyoussef
1 comments posted 18yrs posted by swissiyoussef