I am using a XAUI core in my design for a PCIe board with a Xilinx Virtex - 5 LX110t FPGA. The board specifications require the GTP dual tiles of XAUI to be constrained to locations X0Y0 and X0Y7 which are far from each other on the FPGA. Due to this, the design does not meet timing. The user-guide for the rocketio transceivers suggests modification of channel bonding attributes of the GTP Dual tiles to meet timing. To try this out, the default channel bonding level for the 4 GTP tiles (2 GTP duals) was changed to 3,2,1,0 with 3 as the master tile. This design works fine in simulation, but does not meet timing. The timing error as seen on timing analyzer was due to the rxchanbondo signal.
The channel bond level was further changed to 5,4,1,0 with 5 as the master. Two pipeline stages were added for the rxchanbondo signal (between the tiles 4 and 1). This design meets timing, but does not work in simulation. All these changes were made to the rocketio_wrapper.v file in the XAUI core generated using coregen.
I feel that the wiring between the tiles in the rocketio_wrapper.v file needs to be modified to hook-up all the signals that may have been disturbed due to the addition of the two pipeline stages. Unfortunately I do not have a lot of experience working with rocketio transceivers and their channel bonding attributes which puts me in a state of bother while analyzing what signals need to be modified/ reassigned/patched between the gtp tiles.
I would appreciate any suggestions from anybody who has had experience working with XAUI, rocketio's and their channel bonding attributes.
Thanks for your help in advance