My desig directly instantiates Xilinx block ram ramb16_s18_s18, in order to verify that those block rams have been integrated correctly in the design, I'm using the block ram verilog file from ISE unisim directory to validate my design in simulation, but it seems that there are timing issues when I simulate the design in ModelSim. Are those files supposed to be run correctly in simulation? or they're just for FPGAs.
Thanks, Jack