I want to know which is the right way of implementing and usage of fixed point number data types in hardware(industry standard)..I have referred various FIR implementations where they are mostly handling filter coefficients as integer(truncating from fixed or floating point using MATLAB) or binary.Is it difficult to handle and implement real(fraction) numbers i.e.,filter coefficients values directly in the hardware?
for example:
sample Filter coefficients generated by FDA tool:
fixed point=0.211944580078125 or
16-bit signed integer= 13890 or fixed point binary =0011011001000010
all the above are equivalent but belongs to different data type..Now i am confused which to select for implementation in my code..
Note:
Fixed point representation is looking challenging for some synthesis tool as it not supported. Signed integer looks simple but less accurate Fixed point binary looks tedious..
Pls suggest if anyone knew how to convert fixed point to integer or binary ?using which tool?I suspect MATLAB fixed point tool will be useful but i dont know the procedure..
If i use fixed to integer conversion using left shift operation...I am not sure i may be thrown with compilation error as the maximum long int i can is 2^32 only..
so if i have such a long 0.99999999999999999998888888888888777777777
iit is impossible to have such a big int converted value..
Hi Faza, There are lots of ways of doing this so I doubt there is such a thing as an industry standard. But here is the process I use.
1) Run a fixed point simulation in matlab using the fixed point toolbox. Since for FPGA design there is a direct relationship between wordlength and logic usage my goal of the fixed point simulation is to find the minimum wordlengths that give the required performance. Wordlength is only half the story though.
Determining the right scaling and location of decimal point is the other issue I need to sort out in the fixed point sim. Just imagine a
16 bit unsigned binary number. I can put the decimal point anywhere I want but its a tradeoff between range and quantisation noise. Considering the extremes: with the decimal point at the most left position I can reprsent only a small range of numbers (0->1) but quantisation noise is a minimum. With the decimal point in the right most position I can represent a much larger range (0->65536), but the quantisation noise is now much larger.
In general the range must be large enough to avoid overflow, and more and the quantisation noise is larger than it needs to be.
2) Implement the fixed point model in hardware
The key thing to realise, and I think you almost understand it, is that the hardware representation of these numbers is identical - its just your "real world" interpretation of it that is different in each case. The hardware that uses these three representations is the same for each case. The first two numbers just have the decimal point in a different place, the last one you have not specified the decimal point location at all.
I use VHDL and use the signed/unsigned data type and I use comments to keep track of the decimal point location. The decimal point is 'implied'.
I use the fixed point toolbox fi() function to quantise floating point filter coefficients, and to produce hex strings of the fixed point numbers. The VHDL reads these strings into the design.
Yep, Matlab's fixed point toolbox is great for this. type "help fi" and search the matlab help. e.g. a = fi( 0.213412, 1, 16, 15 ) %signed fixed point number, 16 bits, 15 fractional bits. a.bin %get binary value a.int %get integer value
A number of that precision is probably impractical for a real hardware implementation. You must truncate it. This leads to a tradeoff between how many bits you use in the hardware vs. how closely the real hardware filter matches your desired response.
The first two numbers just have the decimal point in a different place, the last one you have not specified the decimal point location at all.
MATLAB FDA tool is generating the binary equivalent without decimal point similar to fixed point tool..I dont know which is correct among MATLAB ..which i have to use..quantization with truncation is also present in FDA tool
a =3D fi( 0.213412, 1, 16, 15 ) %signed fixed point number, 16 bits, 15 fractional bits. a.bin %get binary value a.int %get integer value
I am wondering if u can guide how to use fprintf for the above as the following gives an error fprintf(outfile1, '%f\n', a);
This leads to a tradeoff between how many bits you use in the hardware vs. how closely the real hardware filter matches your desired response.
My input bits width is 16 coefficient bit width is 16 output width is 40
You continue to demonstrate an extremely weak grasp on simple concepts. While I still encourage you to talk to your professors and *choose another pursuit* for your final year project, I'll point out that your declaration that these tiny 32 bit integers are too small to accommodate your numbers like 0.99999999999999999998888888888888777777777, you state you have 16 bit input widths and 16 bit coefficients. That number is so much larger than 16 bits it's silly.
FIRs need limited size for their operands. You seem to now specify reasonable constraints on your coefficient and data but do you know why those values are chosen or did your professor or Matlab (or paperboy) tell you you needed these realistic values?
Because precision isn't free, all digital filtering has "quantization effects" which can affect the filter characteristics and/or noise generated by your filter, even stability in IIR filters.
You need to know many characteristics of the filter you're trying to implement to properly size an FIR in taps, input width, and coefficient width. It's incomplete to declare a "cutoff frequency" and think you are ready to design. Do you know your required passband ripple? Stopband attenuation? Steepness of your cutoff?
You need to 1) research more what digital filter requirements are needed for your FIR implementation, 2) understand various ways digital filters are implemented (or at least research the FIR), and 3) learn how to do hardware design with FPGAs. This last item will set you back months by my guess.
PLEASE choose another project with which you can succeed.
Hi there, I am implementing IIR filter in VHDL for Spart-3 FPGA Target. have found these packages you mentioned in response to this guy's question very good. But I don't exactly understand how to use these packages? Any other comments welcome. I am designing a butterworth lowpass filter (atm just 2nd order filter). have implemented it in simulink and could generate VHDL code as well but am trying to write the code myself. or atleast with a different approac because that HDL code generated from Simulink just converts th coefficients values manually and treat it as a signed number (converte from an integer value of a fractional binary conversion of a floating poin number). Anyways, If I couldn't explain this Simulink thing very well, then I be ur pardon but it'll be handy if u could tell about that ficed poin packages? And I could discuss this SIMULINK thing further if u wish. Thanks very much, Kami
The packages come with a testbench and documentation that explains how to use them. Read those first, then post more specific questions here if you have any.
I'm not sure the other posts have made this clear, the package described here is not a signal processing tool. It is just a fixed point math library. You still have to figure out how to do the signal processing. This library gives you the low level tools to implement fixed point math in the FPGA.
Hi Rick, Yes that's right. I am trying to implement fixed-point math in VHDL (fo FPGA implementation). and this is for filter coefficients. If I am able t implement that DF-II diagram of the IIR butterworth lowpass filter, won' it be signal processing? I guess so. That's what I am trying to do. I mea perform some additions and multiplications on the input data (which ideall should be a sinusoidal wave or sth but anyhow,) and the filter coefficient which i can take as the constants coz I already know their values. so that's what it basically is. Any comments/suggestions welcome. Much Appreciated, Kami
So the question is, do you understand the signal processing? If you understand that, then you need to analyze the algorithm in fixed point arithmetic before you try to implement it in hardware. I prefer to use fractions for all of my numbers, both the input data and the coefficients. Then the multiply won't overflow. Of course it can underflow, but that is not as hard to handle.
So start by working in floating point arithmetic using numbers between
1 and -1. Then scale this to fixed point values. Once you have the simulation running you can try implementing it in hardware.
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