Field-Programmable Gate Arrays

Xilinx Webpack

Hi all What are the limitations of the free Xilinx Webpack ? Does any one know ? Thanks EC

9 comments posted 18yrs

posted by therightinfo

9 comments posted 18yrs posted by therightinfo

Altera Cyclone II EP2C20F484C6N

I have 240 extra pieces of the Altera EP2C20F484C6N and we will not be able to use. Parts are new in original factory s...

1 comments posted 18yrs

posted by jon

1 comments posted 18yrs posted by jon

Cadence offers to buy Mentor Graphics for $1.45B

http://biz.yahoo.com/ap/080617/cadence_design_mentor_graphics.html

3 comments posted 18yrs

posted by dhschetz

3 comments posted 18yrs posted by dhschetz

Basic Questions about MIG (Memory Interface Generator)

Hi I need little help about ISE MIG tool. I have a couple baic questions and if someone can answer me I would be very g...

3 comments posted 18yrs

posted by Zorjak

3 comments posted 18yrs posted by Zorjak

Xilinx Spartan FPGA BlockRAM in Simulation

My desig directly instantiates Xilinx block ram ramb16_s18_s18, in order to verify that those block rams have been inte...

1 comments posted 18yrs

posted by jack.harvard

1 comments posted 18yrs posted by jack.harvard

Virtex5 FPGA Board and USB interface

Dear all, I am working on a project where I need to store datas on the Flash memory of my FPGA board. I would like to d...

5 comments posted 18yrs

posted by XSterna

5 comments posted 18yrs posted by XSterna

FPGA configuration Beginner questions...

hello as i mentioned earlier, i'm a beginner with fpgas. in fact, this is the first time i'm configuring an fpga.... I...

4 comments posted 18yrs

posted by vikram788

4 comments posted 18yrs posted by vikram788

Base System Builder problem... no board

hello. i use EDK 9.1, and have a XUP Virtex 2 pro development board with me, device: XCV2P30. In Base System Builder, i...

0 comments posted 18yrs

posted by vikram788

0 comments posted 18yrs posted by vikram788

Rocket IO alignment, clocks

Hi all, We are using Rocket IO on Virtex 2 pro and we are facing some problems. 1- What is the user frequency clock ? T...

0 comments posted 18yrs

posted by fpgaasicdesigner

0 comments posted 18yrs posted by fpgaasicdesigner

XAUI v7.2 - timing issue - *channel bonding attributes*

I am using a XAUI core in my design for a PCIe board with a Xilinx Virtex - 5 LX110t FPGA. The board specifications req...

3 comments posted 18yrs

posted by chethanzmail

3 comments posted 18yrs posted by chethanzmail

TXCOMSTART/TXCMOTYPE of V5 SATA GTP with ISE10.1.1

1>is TXCOMSTART/TXCMOTYPE useful? My SATA controller includes OOB generate/detect circuit.During simulation,The V5 SATA...

0 comments posted 18yrs

posted by water9580

0 comments posted 18yrs posted by water9580

Will Modelsim XE 6.3c (Win32) run in Linux/WINE?

I've seen messages from regular posters saying that they run Modelsim/XE Starter Edition in Linux. This evidently works...

5 comments posted 18yrs

posted by akro

5 comments posted 18yrs posted by akro

How to define the Dout width of DA FIR logic Core

Hi, I want to use Xilinx DA FIR logic core (Ver 9.0) to generate many FIR blocks. The wordwidth of Dout is defined as t...

1 comments posted 18yrs

posted by rxjwg98

1 comments posted 18yrs posted by rxjwg98

FPGA IO Pin Unwanted Coupling

Hello, I am fairly new to FPGA design and have a Xilinx Spartan 3 board, that has a 50 pin IO bank. When I load up a de...

2 comments posted 18yrs

posted by WyndyPickle

2 comments posted 18yrs posted by WyndyPickle

Simulate Microblaze in System Generator

Hi. I've spent hours trying to find a simple example/turorial of a microblaze imorted into system generater for simulat...

0 comments posted 18yrs

posted by klauspetersen

0 comments posted 18yrs posted by klauspetersen