Basic Questions about MIG (Memory Interface Generator)

Hi

I need little help about ISE MIG tool. I have a couple baic questions and if someone can answer me I would be very greatfull. First thing I wanted to ask is: "does MIG gives me oportunity to define data bits aslo. I meant, in the UCF file that is generated at the end I can see only control signals. That is ok, yes? than in my design, I can define constraints about DATA ports as I want. Am I right about this?

I also waned to ask one more question. I can reserve pin that I don't want to be used by MIG, but how can I be sure that pins that it has chosed are same every time I generate this core. For example . I want that all NETs are from BANK 1. I put these Bank0 Bank2 adn Bank3 as reserved. But how can I be sure that all Nets are shosen on the same way every time. Can I reserve all pins beisde the ones I want to be used by MIG (reserve also some bits from bank 1). IS it OK. But still I have problems if I am not sure that the pins are reserved the same time (IF I conect ddr and fpga on the pcb I can't change it time to time).

and the last I have some strange problem that I didn't get from the begging. I reserve all banks except the bank 1. When I want to chose pins and when I chech check box indicaitng data pins in bank 1 I get this message.

"MIG doesn't suport data signals that are from multiple sides limit your selection for Data signals for only one side". This confuse me totaly. Should I check All pins that are going to be used by mig to be on one side? Am I right?

I am greatfull for any kind of help. Thanks to everybody. Zoran

Reply to
Zorjak
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I have used MIG2.0, and it definitiely assigned LOC constraints to all pins, including data bits. It doesn't change pin assignments when you re-generate the core, unless you change something in the wizard, like data width or bank selections. I remember some sort of graphical deal in the wizard for bank selection, and of course you want to stay on one side of the die, to avoid long route delays. There was no need to reserve pins. I hope you are reading the User's Guide.

Barry

Reply to
Barry

Thnak you for your answer barry. you were right aobut data pins. Actually I haven't read the ucf file till the end. I've just seen the control bits where are assigned and I didn't even asumed that data pins can be asigned latter in the file. I asumed that there are going to be on the sme place in the file. But OK. It took me a little time to see this but Ihave found some new things. Thank you for your answer.

Have you maybe ever had a problem when you define your MIG core to use it in the ISE project. I have some stupid proablems that ISE don't want to recognize this core althoug I've included xco file in it (I generate the core from the ISE enviroment so all files should be included automaticly). I just want to test this core. I'have jsut made one vhd file copying parts from vvho file that was generated but no. I have problems that ISE says that it can't find my core. I have to rebuid it, and after that many strange things happen. Which is the worst the error that I am getting is not always the sma.e Sometimes ISE ask from me to include all vhd files generated from MIG core generator. ANd when I do this I get 200 warings saying taht sam parts can't be instated. Strenge. I post one more topic here about this problem to explain this.

If you had similar problems, please tell me more about them Thank you very much for all your help Zoran

Reply to
Zorjak

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Sorry, but I use Synplify rather than XST for synthesis. After running coregen, I copy the ngc file into my project directory. Synplify finds it and hooks up the core. Notice that there are two files named .vhd; the larger one is for simulation, and the small one is for synthesis. In one version of coregen, the small one was generated incorrectly, without the empty architecture part. HTH

Reply to
Barry

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