Hi, I want to use Xilinx DA FIR logic core (Ver 9.0) to generate many FIR blocks. The wordwidth of Dout is defined as the following:
DOUT[R-1:0]: FILTER OUTPUT SAMPLE R-bit-wide output sample bus for the FIR, half-band and interpolated filters. R depends on the filter parameters (data precision, coefficient precision, number of taps and coefficient optimization selection) and is always supplied as a full-precision output port to avoid any potential for overflow.
The width of DOUT(R) is out of my control for the many different FIR coefficient sets.
In my project, I would like to have the same output wordwidth of the many DA FIR blocks. Does anyone have some good idea to reach that goal? Thanks a lot.