PLL tricks

e:

ference output stops long term phase shift between the two, but control onl y the relative phase-shift, not the absolute phase shift.

o in this case? There will be a relative measurement and that will be brou ght to zero by the loop. So what is the "absolute" phase shift? Or are yo u talking about the short term phase shift of the VCXO?

er, so long as it long-term averages to less than a picosecond - or whateve r - before it can build up enough to shift the phase of the 155.52MHz VCXO.

e in this circuit. Any deviation will result in noise and phase shift of t he VCXO output. The question is just how large that deviation is. I guess you are saying that the filter can average out the deviations well enough. John seems to think that can cause other problems or maybe he just doesn' t have confidence in this idea because he hasn't played with it yet. He ad mits he is not a math guy and prefers to test and simulate.

MHz data stream, but the flop was clocked at 77.76 MHz. But my new problem is to generate that data stream, and I'm given a 10 MHz source to lock to.

y seen a couple of papers on the subject, not very helpful, and most PLL te xts don't even mention the technique.

s, but the 80 KHz comparison frequency is scary. I was hoping a discussion would suggest a cute way to improve it.

1psec relative stability misses the point that dividing the 155.52MHz down to 80kHz introduces more than a 1psec of phase shift, as doe s dividing 10MHz down to 80kHz.

etermine which edge of the clock to compare, but the comparison would be do ne between the two clocks, not the divided clock. The divided clock would be used as an enable on the phase comparison in effect.

he Dflop can compare that to the un-divided other one. I'll divide in an FP GA but resync with an Eclips flipflop, so the division will add sub-ps jitt er to the overall loop.

than single ones, but I don't have measurements to back that up.

used in IC testing to force metastability.

e

hibit usefully less jitter than one. YMMV.

it is perceived. I don't think you can analyze this circuit to come up w ith a number of MTBF of the synchronizer FF. John said in an earlier post that 100's of ps of metastability won't be a problem, but the nature of met astability is that you can't predict the duration. The best you can hope f or is to characterize the average frequency of failure and in this case the feedback will be pushing the circuit to the point of failure.

As John says, if you can meet the specified setup and hold times for the pa rt, you won't get meta-stability.

You can't do that until the 155.52MHz clock is locked to your 10MHz clock a nd you can pick the occasional clock edge pair - one every 12.5 usec - whic h is exactly lined up, for which he'll probably need a two-stage - acquire lock then synchronise - process, but if you do do this can you can avoid m etastability by careful design.

test the metastability characteristics of a device... that circuit would ha ve a reproducible and defined distribution of the edges being coincident wh ile this one is hard to characterize and is actually trying to maximize met astability.

g-bang loops is sufficient for the purpose at hand. My experience with EC LiPS D flipflops as phase detectors is, *ahem*, limited (read, nonexistent) .

I have used them - and they did work - but the demands were rather cruder. It was in the pulse generator for an electron spin resonance spectrometer, and the old - very hairy - TTL pulse generator had been producing detectabl e sub-nanosecond jitter on the pulse edges. Pushing the signal from TTL int o ECLinPS, resynchronising it and translating the re-sychronised pulse back to into TTL did reduce the jitter to an undetectable level, but "sub-nanao second" is quite a way short of "picosecond".

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Bill Sloman, Sydney

You have snipped too much context. I was the first to propose just that, and that my sin/cos function on opencores.org would be easy to adopt. There even are some TODOs in the VHDL source code already.

exactly.

And I always see here "1 ps jitter" without any qualification. That makes as much sense as "my car consumes 8 liters of Diesel". From here to work? per 100 Km? One hefty accelleration?

Jitter needs measurement bandwidth. When I said that telecom ps are easy, I meant exactly that. They start integrating their phasenoise at 12 KHz or so. All of the 1/f region is therefore ignored, and that is the lion's share.

A friend of mine had made systematic phase noise characterizations when he built frequency synthesizers for avionics and found that ECL in Mosaic 3 process was about the worst that industry had to offer, noisewise.

I find it hard to believe that Mosaic's grand children are suddenly on the other end of the scale. Along with the ultrafast switching comes ultrawide noise bandwidth where one must integrate over many harmonics from DC to daylight.

All people I know who are seriously in timing use Schottky ring mixers as phase detectors and that must have a reason or two.

That does not mean that I dislike ECL. I was an early adoptor of 10KH and 100K, and right now there are many 100EP51 on this table :-)

I would not pin my hopes to high that one could transfer much phase noise cleanliness (is that a word?) from the 10MHz ref to

155MHz. From 10 to 100 MHz the noise goes up 20 dB by principle, from 100 to 150 abt. another 3 dB - and your ref must be better by this, without your self-indroduced errors. It is best to leave the oscillator alone, trying to regulate it is phasenoise-wise an invitation to desaster, as I could see this spring on the E5052B. That thing is a real eye opener. Every change must be slooooow.

And with regard to metastability, IIRC I heard Peter Alfke of Xilinx say something like "The speed you see in an FPGA nowadays is wiring. The speed of the decision loop inside a FF is so fast that metastability just won't happen. One sychronizer stage is enough." I think the sentence contained "lifetime of the universe", also. That was in the Virtex-4 time frame, not now with 13 GBit/s I/O.

:-) LIKE

regards, Gerhard

You sound like you are off your meds again ;)

Care to explain yourself? I wonder if you fully understand metastability.

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Rick

With a DDS chip, this isn't always true, but it is true for the Analog Devices AD9915 - at $145 each you' expect them to work out the modulus for you, which they can't quite manage, but you can set up pretty much any modulus you want.

If you buy the right chip, and the integer you want isn't too big.

The AD9915 limits you to integers smaller than 2^32 - one of them has to be less than 2^31 and another less than 2^32-1.

If you rolled your own you might be less restricted.

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Bill Sloman, Sydney

It produces zero ps of phase shift in the clocks because the divided signal is not used to clock anything. It is used to *enable* the FF that is clocked by one clock and samples the other clock on the D input.

John has said the 80 kHz will be resync'ed to the clock because it comes from the FPGA with a considerable delay, but as long as that delay puts it outside of the setup/hold window the delay has no bearing on the circuit.

You seem to be missing the point of the phase detector. It will be sampling one clock with the other. When the two are in sync the clock edges will be nearly coincident and the FF will be as close as possible to metastability at all times... by design. The goal of the circuit is to put the two clock edges within 1 ps of one another.

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Rick

The only time the dflop phase detector might go metastable is when the VCO and reference edges are exactly aligned. In that case, we don't care whether the flop output goes to 1 or 0, so it may as well flail around for a few ns. At 80 KHz, there's gobs of time for an ECL flop to resolve.

ECL flops resolve fast, and don't do stupid oscillatory stuff like old TTL. 74LS could take many microseconds to settle, and would usually oscillate to boot. Metastability events would make clicks on a nearby FM radio.

And, as I said, it doesn't matter anyhow.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

I'm not sure of all the ramifications of this, but I can tell you that John is just looking at one aspect of the ECL circuit, the timing window in which a transition on the input results in an uncertain output. This is often called the metastable window. John is not worried about the output being metastable. He is concerned by the fact that it would "add" jitter to the sampling process.

I think you are talking about other aspects of ECL jitter such as the timing of the output edge. Turns out that this is not important. He is just trying to sample the two clocks with as little added jitter as possible. Remember, this ECL FF is not used as a clock, it is treated as analog, filtered and used to control the VCXO.

I have quoted Peter on this issue before as well, but it seems some of the newer families of FPGAs have fallen backwards in that regards. It was not from someone as authoritative as Peter, but they were talking about FPGA families Peter never saw so I can't dispute them.

Thanks. Sometimes I can find interesting solutions to interesting problems.

I didn't snip anything this time. ;)

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Rick

"Exactly"? What does that mean? There is no such thing as exact, only exact to within some spec. In this case this window is *exactly* the source of your jitter isn't it? The input transitions at some close time of the clock and instead of being always seen as a '1' is sometimes seen as a '0'. Or is there another source of jitter having to do with fluctuations in the timing of the internal circuit?

I expect with all the filtering it may well not matter much. The 80 kHz doesn't matter so much since you aren't clocking the output. The filtering is what prevents it from affecting the VCCXO.

What is different about the ECL stuff that it wouldn't oscillate? My understanding is that the FF contains what amounts to a ring oscillator if it is put into an unstable condition of a '1' on part of the circuit and a '0' on another they chase each other around. Eventually one catches up with the other and the oscillations stop since the circuit is inherently stable.

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Rick

Actually, there is nothing special about 10 MHz, other than it's a round number. Around 25 Mhz generally results in around the "best" frequency for xtal oscillators. One wants as high a frequency as possible, but higher frequencies have xtal and circuit issues. Its a trade off on best xtal mechanics and circuit characteristics, e.g. pulling, ps sensitivity, power, noise, etc. Hint: I have spent a LOT of time running phase noise simulations on designs over a range of frequencies, over a range of topologies.

9.92Mhz is not a good choice. The standard high performance oscillator xtals are typically design specified for > 10Mhz < 50Mhz They are some speced lower, but this limits choice.

Kevin Aylward

- SuperSpice

What I will say though, is multiplying up by harmonic selection from LC tanks gives orders of lower phase noise/jitter than a PLL.

PLL are useful when you want programmability in frequency and no inductors, but 80 year old LC tank technology blows PLL away in terms of noise performance. For example, meeting -150 dBc (30fs jitter) flat band phase noise at 2.5GHz is, essentially, not achievable with PLL techniques, not that I am giving anything away on one of my current projects...

Kevin Aylward

- SuperSpice

ote:

reference output stops long term phase shift between the two, but control o nly the relative phase-shift, not the absolute phase shift.

two in this case? There will be a relative measurement and that will be br ought to zero by the loop. So what is the "absolute" phase shift? Or are you talking about the short term phase shift of the VCXO?

tter, so long as it long-term averages to less than a picosecond - or whate ver - before it can build up enough to shift the phase of the 155.52MHz VCX O.

ure in this circuit. Any deviation will result in noise and phase shift of the VCXO output. The question is just how large that deviation is. I gue ss you are saying that the filter can average out the deviations well enoug h. John seems to think that can cause other problems or maybe he just does n't have confidence in this idea because he hasn't played with it yet. He admits he is not a math guy and prefers to test and simulate.

2 MHz data stream, but the flop was clocked at 77.76 MHz. But my new proble m is to generate that data stream, and I'm given a 10 MHz source to lock to .

nly seen a couple of papers on the subject, not very helpful, and most PLL texts don't even mention the technique.

ons, but the 80 KHz comparison frequency is scary. I was hoping a discussio n would suggest a cute way to improve it.

does dividing 10MHz down to 80kHz.

That needs thinking about. When I did a similar trick with TTL pulse stream and a 200MHz clock, the propagation delay from the original 200MHz clock w as potentially quite a bit longer than 5nsec, and the difference between le ast delay and worst case delay was more than 5nsec, so I had to allow the u ser to pick the edge of the 200MHz clock that was furthest away from the ac tual TTL transitions.

FPGA's tend to be fast than TTL these days, and synchronous dividers using look-ahead carry can have minimal propagation delays from the clock, but 6.

43 nsec doesn't give you a lot of propagation time. It's a little more than a metre of coax cable (shades of the faster than light neutrinos).

determine which edge of the clock to compare, but the comparison would be done between the two clocks, not the divided clock. The divided clock woul d be used as an enable on the phase comparison in effect.

the Dflop can compare that to the un-divided other one. I'll divide in an FPGA but resync with an Eclips flipflop, so the division will add sub-ps ji tter to the overall loop.

er

's used in IC testing to force metastability.

afe

exhibit usefully less jitter than one. YMMV.

ow it is perceived. I don't think you can analyze this circuit to come up with a number of MTBF of the synchronizer FF. John said in an earlier pos t that 100's of ps of metastability won't be a problem, but the nature of m etastability is that you can't predict the duration. The best you can hope for is to characterize the average frequency of failure and in this case t he feedback will be pushing the circuit to the point of failure.

e part, you won't get meta-stability.

ck and you can pick the occasional clock edge pair - one every 12.5 usec - which is exactly lined up, for which he'll probably need a two-stage - acq uire lock then synchronise - process, but if you do do this can you can avo id metastability by careful design.

No. It's to locate two clock edges within 1 psec of one another.

It's like the type 2 phase detector in the 4046, which has a dead band arou nd perfect synchronisation, so you need to deliberately run it so that it n ormally sits outside the dead-band. Philips improved it in the 9046

as described in page 9,10 and 11.

John does claim to have avoided metastability, so he presumably has done so mething equally clever. One can't entirely discount the possibility that he 's fooling himself, but it's kinder to give him the benefit or the doubt.

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Bill Sloman, Sydney

On a sunny day (Sat, 13 Sep 2014 14:28:39 -0700) it happened John Larkin wrote in :

John, I was thinking last night about this problem, but I quickly, for the 1 ps jitter case, got curious about your 10 MHz reference. For sure that needs to be 'better'. Is it a sinewave? A symmetrical square wave? Rise times?

The flip-flop phase comparators are noisy by themselves, in precise nanosecond locking systems I have worked with, you first lock to frequency with a simple phase comparator, and then after frequency lock switch to a second more precise phase comparator, and sometimes even a third. I have never done a pico second accurate lock. Anyway after frequency lock you switch to the normal PID lock, I have used sample and hold on a ramp for that, so you are in linear range and no 'bang bang' noise is present. If the system is knocked out of lock, then you go back to frequency comparator etc. For the PID case you can set gain and I and D compensation and you like.

s,

shows only -100dBc/Hz on its performance curves.

does have curves that go lower, but only above about 1MHz frequency offset (whatever that means).

John Larkin does have an aversion to inductors, though a useful inductance at 2.5GHz could look very like a spiral track on a PCB.

Making a varactor-tuned 2.41056 GHz external LC oscillator for an AD9915 mi ght be a neat way of getting a tolerably good synthesised 155.52MHz wavefor m - with 15.5 samples per 6.43nsec cycle it wouldn't take much low pass fil tering to get the output looking sinusoidal.

A second AD9915 would be one - rather expensive - way of getting an 10MHz o utput to lock to the 10MHz reference clock

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Bill Sloman, Sydney

But the circuit - as described - is deliberately designed to maximise the chance that the ECL bistable will go into a metastable state.

So John is fooling himself. Presumably it happens rarely enough not to matter much, if his 77MHz to 155.52MHz synchroniser works.

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Bill Sloman, Sydney

looks like you need 2-way time transfer via DLLs and pseudo noise. My current customer does just that from ground to space & back.

??? on page 8 I see the 3 and 4 GHz units break the -150 dBc/Hz at 10 MHz offset, still linearly sinking towards the flat noise floor.

Gerhard

t (whatever that means).

e at 2.5GHz could look very like a spiral track on a PCB.

might be a neat way of getting a tolerably good synthesised 155.52MHz wavef orm - with 15.5 samples per 6.43nsec cycle it wouldn't take much low pass f iltering to get the output looking sinusoidal.

Actually, an external RF oscillator for the AD9915 can present any frequenc y from 500MHz to 2.5GHz. A 2.33288GHz oscillator would give exactly 15 DAC outputs per cycle - it would need low pass filtering, but there wouldn't be any cycle to cycle jitter.

A 1.39968GHz oscillator - 9 times 155.552MHz isn't quite 140 times 10MHz, b ut it's very close. The DAC values in a 10MHz waveform synthesised from tha t would creep very slowly.

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Bill Sloman, Sydney

As I've said, I haven't a clue what those curves mean, and I was deliberately fishing for a tutorial ...

John Larkin talks about keeping his jitter inside 1 psec which isn't the same kind of unit at all.

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Bill Sloman, Sydney

I feel you haven't understood what John is trying to do.

He wants metastability, but in a controlled way that he claims he gets with these device. Where the output goes essentially from logic 0 to logic 1 depending on whether these clocks are early or late by 1ps in a gradual and monotonic manner.

In effect a phase detector with a huge gain. The output is analogue and will be filtered before driving his VCXO.

My concern is that there will be so much other jitter in his system that it will never actually sit in this metastable region.

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Mike Perkins 
Video Solutions Ltd 
www.videosolutions.ltd.uk

Won't LC tanks have horrendous temperature coefficients?

--
Mike Perkins 
Video Solutions Ltd 
www.videosolutions.ltd.uk