If the OP uses a VCXO I wouldn't have thought this would be an issue. Furthermore the filter bandwidth can be tightened after lock.
-- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk
I would agree with up to this point. The idea of having a phase comparator working at 80kHz producing a consistent voltage to drive your VCXO with ps accuracy worries me.
If you mean a 4046 PC2 lookalike, then these will have either an overlap (hysteresis) or no output for low phase error where you 80kHz clock edges are near conincident.
-- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk
Ahmmmm..... 155.52 Mhz is so bog standard that every xtal/oscillator company under the sun has xtals and oscillators in the golden range of 10MHz to 50 Mhz that can be multiplied exactly up. e.g. 38.88Mhz and 19.44MHz. I know, because my company has then in stock, and my current asic design uses them!
"19.44 MHz crystal" gets 2800 hits
I was going to suggest this right off the bat, but assumed they was some system reason why he cant do that.
Kevin Aylward
My box will receive a 10 MHz reference from the customer, from some expensive Symmetrix GPS-disciplined thing. I'll also get a 1 PPS pulse from that, and time-of-day data over Ethernet. It's my job to make OC3-like optical data frames, at 155.52 MHz, that are exact in real time to picoseconds.
Frequency locking isn't difficult. Time locking to picoseconds is.
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
John's using an ECLiPS D-flop as a bang-bang phase detector. Very high gain over a very narrow range (< 1ps apparently), as opposed to the 4046 type, whose gain is VDD/(2 pi). Since the decision time is so short, and its tempco narrow, other perturbations hardly matter.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
I did the ECL bang-bang thing to recover the clock from the 155.52 MHz data stream, but the flop was clocked at 77.76 MHz. But my new problem is to generate that data stream, and I'm given a 10 MHz source to lock to.
As far as math goes, analyzing the bang-bang PLL is messy. I've only seen a couple of papers on the subject, not very helpful, and most PLL texts don't even mention the technique.
I did analyze the one at 77 MHz, making some simplifying assumptions, but the 80 KHz comparison frequency is scary. I was hoping a discussion would suggest a cute way to improve it.
Actually, I only need to divide one of the clocks to 80 KHz; then the Dflop can compare that to the un-divided other one. I'll divide in an FPGA but resync with an Eclips flipflop, so the division will add sub-ps jitter to the overall loop.
Right. The dflop phase detector has such high equivalent gain that the downstream lowpass won't add significant time error.
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Anecdotally, double resynchronizers in different packages are better than single ones, but I don't have measurements to back that up.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
I presume you mean a bang bang phase detector where the clock for the D-Type is driven from the VCO and the D-input is the reference (or possibly visa-versa)?
-- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk
The bang-bang PLL bears a remarkable similarity to the circuit that's used in IC testing to force metastability.
Resyncing the FPGA divider has no hazards, because we can provide safe setup and hold times.
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
So I gather. I'll have to try it meself one of these days-it's sort of like working on the wrong loop polarity with a 4046. ;)
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Farnell doesn't have them. Digikey does. I searched both for 9.720MHz and a couple of other multiples before I posted.
I'm aware that 10MHz is a sweet spot frequency for crystal oscillators. 9.720MHz is close enough to 10MHz that the physics is going to be the same.
19.44MHz is further away, but I'm happy to believe that it's still close enough.-- Bill Sloman, Sydney
Understood. Anecdotally, as I say, two stages of resynchronization exhibit usefully less jitter than one. YMMV.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Unless they coincide with decision period. The nightmare situation is some non-synchronous perturbation on the rails that kicks the 155.52MHz oscillator out of phase (obviously not by much) whenever the perturbation drifts through the decision window.
-- Bill Sloman, Sydney
Not with you there.
I presume the OP will have that in mind and have rails that are stable and know the effect any change on his VCXO.
I'm more concerned over the 10MHz reference and its accuracy. Its rise and fall times, and jitter from superimposed noise.
-- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk
I believe Phil's point is that metastability is a problem no matter how it is perceived. I don't think you can analyze this circuit to come up with a number of MTBF of the synchronizer FF. John said in an earlier post that 100's of ps of metastability won't be a problem, but the nature of metastability is that you can't predict the duration. The best you can hope for is to characterize the average frequency of failure and in this case the feedback will be pushing the circuit to the point of failure.
In fact, that is the difference between this circuit and one built to test the metastability characteristics of a device... that circuit would have a reproducible and defined distribution of the edges being coincident while this one is hard to characterize and is actually trying to maximize metastability.
Adding a second FF to reclock the output of the first *will* greatly improve your MTBF and cost next to nothing relative to the rest of the design. But then the impact of a failure may be insignificant. What happens to the filtered output if the output of the FF is in a random state or even oscillates for some time between the 80 kHz samples?
-- Rick
ence output stops long term phase shift between the two, but control only t he relative phase-shift, not the absolute phase shift.
in this case? There will be a relative measurement and that will be broug ht to zero by the loop. So what is the "absolute" phase shift? Or are you talking about the short term phase shift of the VCXO?
, so long as it long-term averages to less than a picosecond - or whatever
- before it can build up enough to shift the phase of the 155.52MHz VCXO.
in this circuit. Any deviation will result in noise and phase shift of the VCXO output. The question is just how large that deviation is. I guess.
The standard PLL architecture - its just one of the possibilities that Floy d Gardner discussed, but it's ubiquitous in reality - is a second order loo p with the error signal from the phase detector being fed into an integrato r whose output controls the frequency of the VCO.
The integrator isn't a perfect integrator - as Gardner discusses, that woul d make the loop unstable - and in analog implementation this means a resist or in series with the integrating capacitor which breaks the 90 degree phas e lag in the integrator at some appropriate low frequency.
The output of an integrator does "build up". With the "fractional N" approa ch you have to make sure that it doesn't build up enough to shift the phase more than 1psec in the 12.5usec it would take for the "fractional N" colle ction of cancelling timing errors to repeat themselves
enough. John seems to think that can cause other problems or maybe he ju st doesn't have confidence in this idea because he hasn't played with it yet. He admits he is not a math guy and prefers to test and simulate.
z data stream, but the flop was clocked at 77.76 MHz. But my new problem is to generate that data stream, and I'm given a 10 MHz source to lock to.
seen a couple of papers on the subject, not very helpful, and most PLL text s don't even mention the technique.
but the 80 kHz comparison frequency is scary. I was hoping a discussion wo uld suggest a cute way to improve it.
c relative stability misses the point that dividing the 155.52MHz down to 8
0kHz introduces more than a 1psec of phase shift, as does dividing 10MHz do wn to 80kHz.termine which edge of the clock to compare, but the comparison would be do ne between the two clocks, not the divided clock. The divided clock would be used as an enable on the phase comparison in effect.
D-flop can compare that to the un-divided other one. I'll divide in anFPGA but resync with an Eclips flipflop, so the division will add sub-ps jitter to the overall loop.
an single ones, but I don't have measurements to back that up.
bit usefully less jitter than one. YMMV.
Two-stage phase lock loops - which use one set of hardware to get into sync h and another to maintain synch are certainly mentioned in Floyd Gardner's book, though in rather general terms, and he also mentions the "lock detect or" which would be a third set of hardware which tells you whether you shou ld be looking for synchronisation or maintaining it.
Or in John's case, whether he should be letting his psec-accurate time dete ctor adjust the the phase of the 155.52MHz clock.
-- Bill Sloman, Sydney
I was thinking along similar lines but with thermal considerations, where thresholds are likely to change and be dependant on the previous clock timings. That could then induce oscillations from one sample to the next.
I presume any form of ECL is more immune to thermal effects than other logic families?
-- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.uk
That is only true if you don't control both your step size and your modulus. No one ever said you had to use 2^n as a modulus.
Yes, they picked a modulus that worked for them.
BCD or any other combination of divisors. One I designed used an oddball divisor in the lower portion of the accumulator and then a binary counter in the top. This allowed an exact match to all of the audio rates needed. Programming the step size used a simple conversion in software.
-- Rick
I'm pretty confident that John's earlier experience with picosecond bang-bang loops is sufficient for the purpose at hand. My experience with ECLiPS D flipflops as phase detectors is, *ahem*, limited (read, nonexistent).
Cheers
Phil hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Metastability is not a problem for the dflop phase detector. Bring it on!
EclipsLite, driven differentially, has a delay or setup/hold tempco below 1 ps per degree C. A fast CMOS flop might be 10 or so.
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
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