Copper RTD? On a flex PCB? Cool. Copper has a nice linear TC.
Now you need copper thickness control, if the absolute resistance matters.
Do you have a good source for flex PCBs? We have a couple of projects that will use flex, with transmission lines and zigzag inductors, and we'll probably have to iterate some, and experiment with losses and things.
I'm also thinking about making a transmission-line transformer out of flex. Inagine a circle with pigtails extending out opposite sides, primary and secondary windings, and clamping that inside the gap of a pot core.
--
John Larkin Highland Technology, Inc
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
I have too, and I've even done it, but turning stepped waves into perfect sines doesn't 'feel' right. We all know it works, I'm not arguing that, but I've got to calculate stuff to be convinced.
I also mistrust having that filter response in the control loop. It might be fine, I just haven't scratched it out.
As an extreme example, a 10MHz crystal filter would clean things up nicely, but add tens of mS feedback delays if it's really good (Q ~= 1e5).
Understood.
It's a solid topology idea, I just haven't done all the homework.
More often I'm trying to solve novel problems. A long time ago, it was making clean BPSK SS UHF cheaply from a cheap crystal, at micropower, fast-settling, with a lot of other constraints. There simply isn't an equation that outputs a novel topology.
More recently I was tasked loading a device with a ~500A max inrush onto a supply made to trip-out around a tenth of that, with everything COTS and "untouchable," lest the certifications be spoiled. That too was solved with a novel external topology, custom for the application.
For me it's usually topology(/ies) first, then equations to compare performance, then trade-offs / selection between the choices.
Right. It doesn't matter for this iteration. A useful rule of thumb is that 1/2 oz copper is 1 milliohm per square at 25C. This flex has 1/3 ounce, so that's 1.5 milliohm/sq. The pattern has about 62,000 squares, which I know because I wrote a small program that generated the serpentine pattern as a .BMP file, and BLH imported it into Eagle and connected it up.
Dunno if it's good--this is our first try. BLH has their contact info but she's goofing off this afternoon. Their prototype offering is 10 pieces of anything that will fit into a 50 mm square, two layers with solder mask and silk for $85. The film is yellow, so maybe it's even Kapton. ;)
As long as you don't screw it up with impedance discontinuities due to the ferrite coming too close at the apertures, it 'll probably work fine.
Back to measuring the absorption spectra of hen's eggs. ;)
Cheers
Phil
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
hobbs at electrooptical dot net
http://electrooptical.net
Quite so. OTOH calculating the fundamental limits as a function of the crystal Q and transistor noise can be pretty illuminating. A few years ago when I was building stabilized lasers for downhole applications, I had to go into a lot of that stuff, and learned a lot. (Leeson's equation for oscillator noise is sort of the electronic analogue of the Schawlow-Townes minimum line width of a laser.)
If you can't calculate how good it _could_ be, how do you know when you're done? It's a pity to declare victory and leave, when there's another 20 dB available with affordable devices. (Yes, I know about engineering being the art of "good enough for the lowest cost", but better performance is always worth something--you can trade it for a higher selling price, wider spec limits, and/or a quieter life.)
Put a penny into the fusebox, Ralph. ;)
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
hobbs at electrooptical dot net
http://electrooptical.net
It jitters when you phase detect its edges. If you don't, the phase detect or output is sensitized to changes in reference or VCO duty-cycles.
ans the DDS cycles through its DAC codes (as opposed to repeatedly using th e same set over and over), creating a much-lower error frequency and phase error waveform related to the DAC's imperfections.
ries of ramps which can be low-pass filtered out. 15.52 of them per cycle i s actually fairly high frequency noise, and a couple of poles of low pass-f iltering would clean it up considerably.
155.52 MHz is only four octaves up. If you're outputting 10MHz, a couple p oles is just -48dB.
ht be a small residual amplitude error that could translate into a periodic phase shift error which could repeat at 80kHz, which could be problem if y ou used an edge-based phase detector.
Yes, that's what I was suggesting.
But, the product-based detector introduces duty-cycle sensitivity. Drift.
e haven't examined that yet.
would be pushing out a stair-case approximation to 10MHz sine wave, with t he steps on the staircase reflecting 155.52MHz content (plus odd harmonics of 155.52 MHz which would be easy to low pass filter down to negligible pro portions).
om it.
ce.
Yes, that's how you generate 155.52MHz from a 10MHz master reference.
iers, which won't work, since 155.52MHz isn't a harmonic of 10MHz.
Right, so the first impulse is to lock the loop at the GCD of 10MHz and
155.52MHz, 80KHz.
I showed how a multiplier lets the phase detector run at 640KHz, an 8x improvement. More improvement might be possible.
om the 10MHz standard, not using the DDS to output 155.52MHz.
can be locked to an external reference.
Unless on-chip resonators have improved, any in-built VCO will have horribl e jitter compared to an external VCXO.
oosing a 244 divide ratio (anything even from 20 to 510 seems to be on offe r) and let it lock the divided output to the 10MHz reference.
ta sheet tells you how - and with the AD9915 you really can get any rationa l number ratio you want.
d Newark don't have any in stock, though there seem to be three in the UK w orkshop.
ater about doing the reverse, which made room for confusion.
I later understood John was trying to use the DDS to divide the 155.52MHz feedback signal to 10MHz so he could run the PLL phase detector at 10MHz.
That adds an awful lot of circuitry and delay into the signal path--I'd think that would jitter.
outputting a 15.52 step 10MHz "sinewave." 15.52 steps is a pretty rough w aveform.
Not to ppm, and if you try you may destabilize the PLL.
ng signal.
a varying analog ramp delay. That would let you keep a much higher refere nce frequency.
rnating the divider modulii.
synthesised 10MHz.
clock with at least the sort of stability you can get from a good quality 1
0MHz quartz crystal reference oscillator. There are quite a few ways to get from A to B.
MHz sq. wave, TTL Comp., 5 MHz to 20 MHz sine wave." an output which could be an exact integer sub-multiple of 155.52MHz. An output at 9.7200MHz might be handy.
That uses a rubidium source to discipline a programmable VCXO, where the short-term phase performance is limited by the VCXO.
That costs a ton in power and complexity, but has no better phase performan ce than my scheme: disciplining an 80MHz VCXO to the 10MHz master, then dividing to 640KHz and running the PLL detector there.
tiple of 155.52MHz. Caesium - at 9.193 GHz - isn't any better.
The worked as well, while saving an order of magnitude in space, delay, power, and money.
kage.
No. The MC100ep195 generates inexactly-spaced edges that jitter and drift. My scheme produces exactly-spaced edges with minimal jitter. Phase drift would be phase detector-limited.
0psec resolution means that it's never going to be good for direct synthesi s, but it would probably be good enough for a good-enough-for-long-term-sta bility scheme for generating a monitoring 10MHz output from the 155.52MHz s ource to be compared with the 10MHz reference crystal by a product detector feeding back through low-pass filter into a nice slow integrator to keep t he VCO at the right frequency in the long term.
If the 155.52 MHz VCXO's short-term stability is that good then there's no need to up the phase detector frequency in the first place. Just run at
80KHz and be done with it.
That might actually be a viable solution: use a really good 155.52MHz VCXO, one that doesn't need to be disciplined that often.
n-integer multiple of the output frequency, say, 250MHz, a DDS could produc e a stair-stepped 960KHz (=155.52e6/162) approximation to a sinewave (for the 155.52MHz PLL) reference, with ~260 steps in it.
easily-filtered DAC-error beat frequency component that might be small enou gh not to matter.
, but for eight units, what you pay for the off-the-shelf solution is recov ered in reduced design time. $1,144.80 doesn't buy a lot of design time.
and the non-binary modulus it offers seems to get rid of the DAC-error bea t frequency component.
Where do you get the 2.44GHz?
ISTM phase jitter using the internal clock multiplier would be awful. If y ou use the external clock, you've merely added the problem of making 2.44GHz.
Additionally (provided you get the DDS to "hit" 10MHz sufficiently exactly) consider removing part of the steps in the "stairstep" DAC output by "blanking them out" with something like this:
formatting link
(warning: messy handwriting)
The whole thing is essentially a "track and resonate" circuit - like a classic "track and hold", but with the "hold" part replaced by a free running resonator (quartz or LC or whatever kind suits you best).
The idea is to move the main part of the noise spectrum from 155-ish MHz and its multiples to a higher frequency (250-ish MHz or as high as the switch will do) and its multiples in order to make filtering easier. In theory one could move the noise into the GHz, but hardly any real world analog switch will be able to drive so narrow pulses. If a PO3B3305A can hit anything above 250MHz that's probably as high as reasonably expectable. At low frequencies something like this should be really easy, but your required frequency is really pushing it.
Of course it's more of a wild guess than a real design and it depends on an already very fast analog switch, driven to the limit of its switching rate, to be "fast enough" - which i'm not entirely sure that it will be. Anyway, maybe it gives you some ideas...
Why does it have to be a binary DDS? This has already been discussed here that you can make a DDS roll over at any number you want. I believe someone already did the math for you. I simply pointed out a few optimizations that would be useful if you were using it to synthesize a sine wave.
Now you are talking about producing a clock which is idiot simple really. In fact this circuit is no longer a DDS, but rather what I believe is called an NCO... don't hold me to that term, I find there are many names for these rather similar circuits and I can't keep them all straight. The point is, yes, you can produce a 10 MHz clock *exactly* from your 155.52 MHz reference. You can also get a remainder at the time of the clock if you want to use that to trim your VCXO.
Sort of related: European starlings (Sturnus vulgaris) develop about
10 to 15 W of metabolic power, and deliver about 1 to 2.5 W at the wings. I hadn't thought about it much before I read the paper, but I was suprised at how small those numbers are. It's almost like the design has been iterated for millions of years, or something. :) (Reference:
Unless I'm mistaking your meaning, all that does is change the duty cycle.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
hobbs at electrooptical dot net
http://electrooptical.net
been great mechanical and otherwise-thinkers and tinkerers too.
At a diner, IIRC.
duplicate, and sometimes refine it.
thought
stuff
people
noiseless
signal.
varying analog ramp delay. That would let you keep a much higher reference frequency.
alternating the divider modulii.
DAC
a
phase-adjust the DDS output by adding a small DAC'd correction. I think that works. (I'm not sure of all the numbers and trade-offs without actually calculating.)
cancel the post-phase detector ripple might be clean circuitry-wise. A dual DDS might provide both.
reference, right?
Running the PD at 10 MHz is not necessarily a win. The capture frequency range is rather small. Indeed some SONET equipment regenerates clock from line rather than a local master clock. Classic case, if the line rate is conditioned by a Cesium standard and the best you have is a OCXO standard. The system is designed to handle these situations. You might even want a
you could get a tidier result by adding 5 when the P < 8 (= 16 -5 -3 ) and 8 ( = 5 + 3 ) otherwise.
Or possibly simpler add 8 on the clock after a carry (falling edge of the high bit) and 5 otherwise, that leaves a gap in the P values at 5 ,6,7 so you'd need to chop the wave table into two parts,
thus if you need to divide by pi you can get very close with a 355 valued phase accumulator and a step of 133.
Digital dividers generate rather precise and stable duty cycles. That's rea lly unlikely to be a problem.
The product detector is going to have some kind of DC off-set - like every op amp in the analog signal processing chain that converts it's output into a DC voltage to control the VCO - but it's going to be small and pretty st able.
We haven't examined that yet.
DS would be pushing out a stair-case approximation to 10MHz sine wave, with the steps on the staircase reflecting 155.52MHz content (plus odd harmonic s of 155.52 MHz which would be easy to low pass filter down to negligible p roportions).
from it.
ence.
There's a cause and effect implication in your choice of words that strikes me a potentially misleading.
pliers, which won't work, since 155.52MHz isn't a harmonic of 10MHz.
Obviously.
from the 10MHz standard, not using the DDS to output 155.52MHz.
ch can be locked to an external reference.
ble jitter compared to an external VCXO.
The AD9915 offers a tenfold faster VCO than the one you had in mind. The da ta sheet provides a lot of data on pages 13 and 14 of the data sheet on the phase noise performance, but in dBc/Hz, which doesn't mean anything to me . The phase noise is unlikely to be impressive, but the on-chip VCO is rest ricted to the range 2.4 to 2.5GHz, so it is probably better than the number you first thought of.
choosing a 244 divide ratio (anything even from 20 to 510 seems to be on of fer) and let it lock the divided output to the 10MHz reference.
data sheet tells you how - and with the AD9915 you really can get any ratio nal number ratio you want.
and Newark don't have any in stock, though there seem to be three in the UK workshop.
later about doing the reverse, which made room for confusion.
The extra circuitry is all in the path that leads to a slowly varying - ess entially DC signal - that control his 155.52MHz VCO or - better - VCXO (whi ch it looks as if he can buy off the shelf from ON-Semiconductor - give or take the usual nonsense about minimum order quantities, and the actual exis tence of physical stock sitting on physical shelves).
Any jitter in that path can get filtered out. You can actually stabilise th e PLL feedback loop despite having a lot of delay in the filters before and after the phase detector. Floyd M Gardner walks you through it in "Phaselo ck Techniques" and I'm sure that there are more modern texts which do it mo re painlessly.
is outputting a 15.52 step 10MHz "sinewave." 15.52 steps is a pretty rough waveform.
Only if you don't understand PLL design.
ting signal.
us a varying analog ramp delay. That would let you keep a much higher refe rence frequency.
ternating the divider modulii.
a synthesised 10MHz.
z clock with at least the sort of stability you can get from a good quality 10MHz quartz crystal reference oscillator. There are quite a few ways to g et from A to B.
0 MHz sq. wave, TTL Comp., 5 MHz to 20 MHz sine wave." an output which coul d be an exact integer sub-multiple of 155.52MHz. An output at 9.7200MHz mig ht be handy.
ance
The power is inconsequential. The complexity is pretty much all inside the module you buy from Freqelec - or whichever of it's competitors you might c hoose to go for. If John only needs to make eight or whatever it is, buying in the complexity is usually a good idea.
The Freqelec package seems to incorporate a 50.255MHz VCO (probably a VCXO) which is unlikely to be much different to your 80MHz VCXO or the 155.52MHz VCXO that John probably ought to buy from ON-Semiconductor (if he can and if it really is a good quality VCXO).
ultiple of 155.52MHz. Caesium - at 9.193 GHz - isn't any better.
But it has to be designed in detail, laid out onto a board and so forth. It strikes me as adding a lot of complexity while not offering all that much in the way of advantage.
ackage.
.
But in a signal path that ends up at the slowly changing DC voltage the con trol the VCXO frequency output. The fact that the nominally 2.5nsec to 8.9n sec delay through the MC100ep195 would increase as part got hotter does imp ose a temperature dependent phase shift between the 10MHz reference and the 155.52MHz VCXO output, but there are similar propagation delays through an y collection of logic.
There are propagation delays through your divider set-up. Not knowing what logic family (or programmable logic device) you have in mind, I can't say w hether they are better or worse, but I do know that they aren't in a signal path where the jitter adds directly to the jitter on the output of the 155 .52MHz VCXO. That path is in there to keep the frequency right,and when disciplini ng a VCXO the bandwidth of the feed-back loop is usually kept pretty low.
10psec resolution means that it's never going to be good for direct synthe sis, but it would probably be good enough for a good-enough-for-long-term-s tability scheme for generating a monitoring 10MHz output from the 155.52MHz source to be compared with the 10MHz reference crystal by a product detect or feeding back through low-pass filter into a nice slow integrator to keep the VCO at the right frequency in the long term.
o
True, but this thread is all about letting John do it faster.
O,
It needs to be disciplined continuously but the optimal bandwidth for the P LL feedback path does depend on the long term stability of the crystal osci llator.
non-integer multiple of the output frequency, say, 250MHz, a DDS could prod uce a stair-stepped 960KHz (=155.52e6/162) approximation to a sinewave (f or the 155.52MHz PLL) reference, with ~260 steps in it.
o-easily-filtered DAC-error beat frequency component that might be small en ough not to matter.
ap, but for eight units, what you pay for the off-the-shelf solution is rec overed in reduced design time. $1,144.80 doesn't buy a lot of design time.
- and the non-binary modulus it offers seems to get rid of the DAC-error b eat frequency component.
244 times 10MHz. The AD9915 VCO can be run anywhere in the narrow range 2.4 GHz to 2.5GHz, which means that the divider ratios that you are allowed to program are 240, 242, 244, 246, 248 and 250. Something in the middle seemed a sensible choice.
I posted a link to the data sheet. You could have worked out how awful it w as - if you know what dBc/Hz actually means - by looking at pages 13 and 1
4
2.44GHz.
Well, you can use any external clock frequency up 2.5GHz. Back in the 1980s you could buy very nice (if bulky and non-cheap) YIG-tuned oscillators tha t ran that fast. Chemically thinned quartz oscillator crystals seem to go u p to about 700MHz, and SAW devices do seem to be able to go quite a lot fas ter, though I've never been motivated to dig into them.
I imagine that if the AD9915 VCO is as bad as you expect it to be, that app roach stops making sense. The AD9915 isn't the only DDS that Analog Devices makes with a built-in VCO, and Linear Technology has a fractional-N part w ith a VCO that runs even faster
formatting link
The Linear Technology VCO offers four over-lapping frequency ranges, each o ne a lot wider the AD9915's 2.4 to 2.5GHz - LT's lowest range is 2.240 to 3 .740GHz which does suggest that their tank circuit has a lower Q than the A D9915's.
All design involves balancing costs and benefits. I'm not interested enough to work out what dBc/Hz actually mean, but it looks as if you aren't eithe r, and John would be out of his depth if he tried to find out.
Some of the people who post here are probably clever enough - or at least d eep enough into working out noise floors - that we can hope for an illumina ting response from them.
Phil Hobbs would probably be happy to advertise expertise in that area, and could well have it.
The picosecond timing accuracy can only between successive cycles of the 15
5.52MHz VCXO, and you maintain that by maintaining the VCXO frequency stabi lity at precisely 155.5200000 MHz vis a vis a 10.0000 MHz crystal clock.
The PPL loop that ties the 155.52MHz VCXO output to the 10MHz reference out put stops long term phase shift between the two, but control only the relat ive phase-shift, not the absolute phase shift.
Short term phase jitter inside the PLL feedback path doesn't matter, so lon g as it long-term averages to less than a picosecond - or whatever - before it can build up enough to shift the phase of the 155.52MHz VCXO.
The fact that a phase detector operating at 80kHz could have a 1psec relati ve stability misses the point that dividing the 155.52MHz down to 80kHz int roduces more than a 1psec of phase shift, as does dividing 10MHz down to 80 kHz.
Insisting on 1psec absolute cycle to cycle stability in the phase detector, ignores all of that, and the delays through the filtering after the phase detector which is absolutely necessary if the noise on the phase detector o utput isn't going to produce phase noise on the sine wave coming out of the VCXO.
picosecond time stability, and it looks like it must work at 80 KHz. As Ph il suggests, it could be the DC part of a compound loop.
A product detector is going to have a similar timing stability, even if it doesn't have data-sheet entries saying what they are, and it's going to be a lot less sensitive to local noise sources (like spikes on the rails) beca use they average out, rather than being broad-band sampled at switching tim e.
Concentrating on the propagation delays in the phase detector, while ignori ng the propagation delays in the components feeding it, and those processin g its output, does look rather like tunnel-vision.
I don't follow this at all. What is the difference between the two in this case? There will be a relative measurement and that will be brought to zero by the loop. So what is the "absolute" phase shift? Or are you talking about the short term phase shift of the VCXO?
That is not clear to me. "Build up" is not something I can picture in this circuit. Any deviation will result in noise and phase shift of the VCXO output. The question is just how large that deviation is. I guess you are saying that the filter can average out the deviations well enough. John seems to think that can cause other problems or maybe he just doesn't have confidence in this idea because he hasn't played with it yet. He admits he is not a math guy and prefers to test and simulate.
What I read was that John would divide one of the frequencies to determine which edge of the clock to compare, but the comparison would be done between the two clocks, not the divided clock. The divided clock would be used as an enable on the phase comparison in effect.
You can't do any better than the phase comparator. So I can see why he want's that as good as possible. But the delays introduced *after* the phase comparator will not produce phase errors. That delay is only of consequence to the loop stability.
Why not go out and buy a 9.7200MHz +/-10ppm crystal, and lock your 155.52MHz VCXO to that via a divide-by-sixteen counter?
You'll have to have your eight crystals ground to give exactly the right frequencies, but there are small businesses that make a living out of producing bespoke crystals.
The stability and so forth should be close to what you get out of the standard 10MHz crystal, and the circuit that you need should be a lot simpler.
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