nd the same from one cycle to the next. As I said, it can create a static p hase shift, but no noise or drift. In the fractional-N at 10MHz system, suc cessive cycles will have different phase shifts - within a 6.4nsec window - but that will repeat exactly every 12.5usec, and most of it will cancel ou t a lot more rapidly.
I didn't think that I was saying it was. I did say it was the same from one cycle to the next, but the cycles I had in mind were the 12.5usec over whi ch the full cycle repeats itself. For the DDS creating 10MHz from 155.52MHz every two periods of the 10MHz look pretty similar, which means that any k ind of decent low pass filtering won't have all that much crap to get rid o f.
Your "0.1% precision" demand comes from *you* not doing the math.
The thread opened with John Larkin pointing out that his problem could be s olved exactly by dividing both clocks down to 80kHz, so here the noise prof ile is going to be repetitive at 80kHz. A big chunk repeats at 5MHz, and my first cut at a solution suggest that most of the rest repeated at 1MHz.
--
Bill Sloman, Sydney
>
>
>
> Somewhat interestingly, when John Wells of Marconi invented the delta-sig
ma
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> approach to synthesisers, it don't seem that the bigger picture of where
>
> that approach sat was known. To wit, recognising the binomial expansion o
f
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> (1-z)^n to get the best approximating delay co-efficients and its relatio
n
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> to ADC.
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>
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> Kevin Aylward
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> www.kevinaylward.co.uk
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> www.anasoft.co.uk - SuperSpice
There's nothing wrong with mechanics, and nothing wrong with fiddling or accidental solutions. Design is, fundamentally, fiddling, namely exploring an enormous solution space and finding something that works well. Brains can do that, somehow. Fiddling is an acquired skill.
Equations seldom design stuff.
One similar textbook technique is to use a dual-modulus divider and, off to the side, compute a DAC value as a jitter compensation. The DAC analog output is summed into the phase detector analog output, to compensate for the small phase jumps inherent in the dual-modulus math.
I think that a DDS thing might work that way too. If we use the MSB (ie, rollover) of a phase accumulator as a scaled-down clock, it has a jitter of one input clock p-p. But, at DDS accumulator overflow time, we know the values of the lower-down bits of the phase accumulator, and they could be used to compensate for the MSB jitter. Somehow.
Does that make sense?
But it still won't allow me to make exactly 10 MHz from a binary DDS clocked at 155.52.
--
John Larkin Highland Technology, Inc
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
Sure. You can compute what the filtered DAC output ought to produce, and use that. With your DDG chops, you could do that standing on your head.
I still think the local feedback approach (offset analogue loop disciplined by 80 kHz bang-bang loop to control drift) would be a cool thing to build.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
hobbs at electrooptical dot net
http://electrooptical.net
What we require is to equate 155.52MHz with 10MHz, such that after
15.552 clock cycles we can produce exactly a single cycle of a sine wave.
Lets suppose we have a sine table that is comprises of 1,944 points with an amplitude of say 255 for use with an 8 bit DAC.
V(n) = 255 * sin( 360 * n / 1,944)
We can load this into block memory of a FPGA.
For every clock at 155.52MHz we advance the phase by adding 125 to the accumulator that counts modulo 1,944.
After 15.52 clocks (or 100ns) we would on average have moved along the whole of the phase table and so output a complete cycle of sine-wave.
The DAC would be driven by the amplitude corresponding to the accumulator/position in the phase table. We can filter to remove higher harmonics to leave a healthy 10MHz sine wave.
We can compare with this single cycle (with a 100ns period) with the cycle we have from the reference 10MHz using a phase comparator.
We have all come across DDS's that use a binary count, but there is no reason why the count can't be modulo an alternative number. Of course the phase table length must suit.
--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk
I was kidding of course. The best designers I've known have always been great mechanical and otherwise-thinkers and tinkerers too.
Feynman made one of his breakthroughs imagining twirling pie plates. At a diner, IIRC.
Yes. And lots of fiddling at an early age helps.
Yep. Equations usually describe stuff someone already did, help others duplicate, and sometimes refine it.
[...]
Yes, that was my 2nd suggestion.
It does. If you had access to the lower bits you could, in theory, phase-adjust the DDS output by adding a small DAC'd correction. I think that works. (I'm not sure of all the numbers and trade-offs without actually calculating.)
A DDS to generate a reference signal, then a separate generator to cancel the post-phase detector ripple might be clean circuitry-wise. A dual DDS might provide both.
But the goal's the opposite, to lock the 155.52e6 to the 10e7 reference, right?
I thought about it jogging. The fractional division using analog ramps would take two ramps--a pre- and post-delay--and some logic.
It's easier and less jittery (I think) with digital equivalents.
To wit, divide 155.52e6 by 243 to get 640KHz.
10 MHz divided by 15 5/8 = 640KHz. So, if you can generate 1/8ths of 10MHz, you're golden.
I mulled a bunch of schemes to generate (n/8)-length pulses for n=0..7, but I think the lowest jitter is to generate 80MHz with a good rock, phase-locked to the 10MHz reference. Then divide by 155 and Bob's yer uncle.
Good VHF rocks are awesome, in my admittedly dim recollection of some old RF Design articles by Matthys(sp?), and 80MHz is well in reasonable range.
The benefit is an 8x increase in reference frequency, and reference pulses that are exact to within the jitter of a very nice rock.
If the 80MHz drifts in phase relative to the 10MHz, the 155.52e6 output drifts too, possibly a problem...
It helps if the brain is well stocked with design solutions.
John's told him that a DDS output would be "jittery". If it had been better stocked, it would have told him that DDS would be pushing out a stair-case approximation to 10MHz sine wave, with the steps on the staircase reflecti ng 155.52MHz content (plus odd harmonics of 155.52 MHz)which would be easy to low pass filter down to negligible proportions. As the undesired content is mostly at precisely 155.52MHz, a notch filter wouldn't have been out of place.
D
nal.
ying analog ramp delay. That would let you keep a much higher reference fr equency.
g the divider modulii.
That's in the same ball-park as using a DDS to go from 155.52MHz to a synth esised 10MHz.
The difference between the staircase the DDS gives John and the sine wave h e want are a series of short (6.4nsec) ramps.
You've got to low pass filter the synthesised 10MHz to reduce the 155.52MHz content (and the additional odd harmonic content). Four poles would pull t hat down by 90dB, and it's all a whole lot less messy than a ramp, though D DS chips are expensive.
better would be to use a
formatting link
to generate a compensating programmable delay in the range 0 to 6.43nsec - actually 2.5 to 8.93nsec.
It only offers 10psec resolution and the accuracy is rubbish, so the phase- detector output will still have some high frequency noise, but you are only interested in the DC content of that output, and any PLL feedback to a VCO has lots of low-pass filtering.
It's the kind of thing that you could do with a really dumb 1944-entry look
-up table. I couldn't buy any ECL RAM from anywhere last time I tried, but the look-up table is only being looked up at 10MHz, and the MC100EP195 data inputs can be driven from any one of " ECL, CMOS, or TTL".
The are programmable logic devices with ECL-compatible outputs - ten might be a drag, but getting the ten bits out serially once every 100nsec wouldn' t be a problem. A look-up table is the dumbest possible way of doing the jo b - an accumulator structure would make much more sense.
Why not stay in the digital domain? It's less messy, and less demanding EMC
-wise.
Sure it will. But the "exactly" 10MHz generated has 155.5.2MHz (and odd har monics of 155.52MHz) components, which you have to low pass filter out. Sin ce 155.52MHz is quite a bit higher than 10MHz a four or six pole low pass f ilter could do a pretty thorough job.
The MC100EP195 would let you get a lot closer to 10MHz entirely in the digi tal domain, but with not less than 10psec of jitter. Since there's up to 1.
5nsec of temperature-dependent drift (from -40C to 85C) on the longer delay s, you'd probably have closer to 1nsec of jitter on the synthesised 10MHz, which would show up as noise on the raw phase detector output.
There wouldn't be any frequency content in that noise below 80kHz, but you can low-pass filter the phase-detector output pretty fiercely before you fe ed it back to the voltage-controlled 155.52MHz oscillator, so it shouldn't be a problem.
I'm not sure what "though most FPGA would only play ball at fundamental" means. 155 MHz is not anywhere near the upper speed limit for signals in a modern FPGA including I/O. Signals feeding a DAC at these speeds are often LVDS anyway and can easily handle two or three times this rate.
Once your design approaches the upper speed range of the FPGA internally, it is quite easy to improve performance by doing multiple calculations in parallel such as the DDR interface you mention would typically use.
Since this is a fixed rate design which does not need programmability of the step size, it would be simpler to use an incrementer (or decrementer) which is loaded with a non-zero start count and is reloaded on reaching zero. The stored data in the table can be permuted to account for this.
The result would be a faster circuit and a simpler circuit.
Another optimization is to separate the upper two bits of the counter to be a divide by four and the lower bits a counter with 486 states. The lower counter creates a ramp and the upper counter bits are used to invert the lower counter as well as the sign bit of the data from the table giving more resolution without using a larger table.
In fact non-binary DDS circuits are not at all uncommon. My test fixture uses one to generate the sine wave while testing our production boards. It tests a 24 bit CODEC so I wanted to get as much resolution as I could and the FPGA is rather small with very limited block RAM.
And in either case the phase step per clock step is an integer. If the quanta of frequency/phase step is the same for 1 LSB the frequencies will be the same. That is what i was talking about. You can keep changing that integer a little bit and introduce a new phase noise at a much higher frequency than the reference phase clock phase noise. Maybe some noise shaping can be done to bury the true reference jitter in another phase noise that gets removed. If Phill H. did the math for it, i might not be able to follow it.
phase-adjust the DDS output by adding a small DAC'd correction. I think that works. (I'm not sure of all the numbers and trade-offs without actually calculating.)
cancel the post-phase detector ripple might be clean circuitry-wise. A dual DDS might provide both.
I really like the possibilities in a dual DDS system. DDS synth 80 kHz or
800 kHz for more prelock bandwidth. (probably not needed or wanted) It looks real straight forward and clean with good opportunities to minimize phase noise.
It is. The DDS outputs a quantized waveform that can be pretty rough. The output is not an exact integer multiple of the DDS' clock, which means the DDS cycles through its DAC codes (as opposed to repeatedly using the same s et over and over), creating a much-lower error frequency and phase error wa veform related to the DAC's imperfections.
The DAC might be very good to where its inaccuracies are acceptable. We ha ven't examined that yet.
ushing out a stair-case approximation to 10MHz sine wave, with the steps on the staircase reflecting 155.52MHz content (plus odd harmonics of 155.52 M Hz
The 10MHz is the master reference; we're trying to generate 155.52e6 from i t.
I'm talking about using the DDS to synthesize a PLL reference signal from t he 10MHz standard, not using the DDS to output 155.52MHz.
John asked to synthesize 155.52 from 10MHz originally but did comment later about doing the reverse, which made room for confusion.
If the DDS is synthesizing 10MHz from a 155.52MHz reference, the DDS is out putting a 15.52 step 10MHz "sinewave." 15.52 steps is a pretty rough wavef orm.
[...]
ignal.
arying analog ramp delay. That would let you keep a much higher reference frequency.
ing the divider modulii.
thesised 10MHz.
We're solving different problems.
I'm talking about synthesizing a low-jitter reference frequency from the 10 MHz master, at a higher-than-GCD frequency (640KHz instead of 80KHz in this example). .------------------------------. .------. | ___ ___ | | ref. | | / \ .---. / \ |
Raising the reference by "n" means we can push the VCXO back towards correc t phase n-times more frequently, lowering its phase wander/jitter w.r.t. th e 10MHz master reference.
Before jogging, I was suggesting an *exact* non-integer divider with consis tent (if imperfect) intermediate timing edges could be produced using - integer numbers of 10MHz clock-cycles, - stretched to the desired pulsewidth with analog digital delay generators .
The edge-timing imperfections could be small, and would be attenuated by th e loop LPF.
After jogging I suggested as simpler: locking an 80MHz rock to the 10MHz ma ster, then digitally dividing by 125, yielding a solid 640KHz reference for the 155.52MHz loop.
The reference edges are then perfectly-timed (i.e., not quantized or approx imated), and stable as the (excellent) 80MHz rock.
All of that's old-school, meant to be solid and simple. '57 Chevy.
Today, a DDS PLL-reference generator might be simpler. Clocked at a non-in teger multiple of the output frequency, say, 250MHz, a DDS could produce a stair-stepped 960KHz (=155.52e6/162) approximation to a sinewave (for the 155.52MHz PLL) reference, with ~260 steps in it.
There'd be a lot of easily-filtered 250MHz in the output, and a not-so-easi ly-filtered DAC-error beat frequency component that might be small enough n ot to matter.
Technically speaking, it isn't "jittering". The artifacts are deterministic , rather than random.
s the DDS cycles through its DAC codes (as opposed to repeatedly using the same set over and over), creating a much-lower error frequency and phase er ror waveform related to the DAC's imperfections.
Considered as an error signal on the perfect sine wave desired, it's a seri es of ramps which can be low-pass filtered out. 15.52 of them per cycle is actually fairly high frequency noise, and a couple of poles of low pass-fil tering would clean it up considerably.
It won't create any kind of frequency error. I can imagine that there might be a small residual amplitude error that could translate into a periodic p hase shift error which could repeat at 80kHz, which could be problem if you used an edge-based phase detector.
With a product-based phase detector, this would average out a lot faster.
haven't examined that yet.
ould be pushing out a stair-case approximation to 10MHz sine wave, with the steps on the staircase reflecting 155.52MHz content (plus odd harmonics of 155.52 MHz which would be easy to low pass filter down to negligible propo rtions).
it.
Not exactly. You are trying to lock a 155.52MHz output to a 10MHz reference .
Trying to generate 155.52MHz from it produces images of frequency multiplie rs, which won't work, since 155.52MHz isn't a harmonic of 10MHz.
the 10MHz standard, not using the DDS to output 155.52MHz.
The only way you can do that is by buying a DDS with a built-in VCO which c an be locked to an external reference.
formatting link
offers a 2.4 to 2.5GHz VCO which you could set at precisely 2.44GHz by choo sing a 244 divide ratio (anything even from 20 to 510 seems to be on offer) and let it lock the divided output to the 10MHz reference.
You can then program any output frequency you want - page 17/18 of the data sheet tells you how - and with the AD9915 you really can get any rational number ratio you want.
Sadly, the AD9915 is expensive - $143.10 each for 5 to 9 from Newark - and Newark don't have any in stock, though there seem to be three in the UK wor kshop.
er about doing the reverse, which made room for confusion.
It's quite a bit cheaper.
utputting a 15.52 step 10MHz "sinewave." 15.52 steps is a pretty rough wav eform.
But a low pass filter would clean it up a lot.
signal.
varying analog ramp delay. That would let you keep a much higher referenc e frequency.
ating the divider modulii.
ynthesised 10MHz.
Depends how high you get above the playing field. John wants a 155.52MHz cl ock with at least the sort of stability you can get from a good quality 10M Hz quartz crystal reference oscillator. There are quite a few ways to get f rom A to B.
formatting link
offers even better frequency stability and - with option 008 "1 Hz to 10 MH z sq. wave, TTL Comp., 5 MHz to 20 MHz sine wave." an output which could be an exact integer sub-multiple of 155.52MHz. An output at 9.7200MHz might b e handy.
Sadly, the rubidium reference frequency at 6.835GHz isn't an integral multi ple of 155.52MHz. Caesium - at 9.193 GHz - isn't any better.
And clumsy. The MC100EP195 could do the same kind of job in a smaller packa ge. The temperature sensitivity of the delay it generates is nasty, and the 10psec resolution means that it's never going to be good for direct synthe sis, but it would probably be good enough for a good-enough-for-long-term-s tability scheme for generating a monitoring 10MHz output from the 155.52MHz source to be compared with the 10MHz reference crystal by a product detect or feeding back through low-pass filter into a nice slow integrator to keep the VCO at the right frequency in the long term.
integer multiple of the output frequency, say, 250MHz, a DDS could produce a stair-stepped 960KHz (=155.52e6/162) approximation to a sinewave (for t he 155.52MHz PLL) reference, with ~260 steps in it.
sily-filtered DAC-error beat frequency component that might be small enough not to matter.
The AD9915 is off the shelf and pretty much complete. $143.10 isn't cheap, but for eight units, what you pay for the off-the-shelf solution is recover ed in reduced design time. $1,144.80 doesn't buy a lot of design time.
It's faster than the number you had in mind - at 2.44GHz versus 250MHz - a nd the non-binary modulus it offers seems to get rid of the DAC-error beat frequency component.
That does sound nice, some fast RFish loop with the bangbang to servo the picosecond precision. We might have to do that if the brute-force
80K bangbang gets into trouble.
A cheapish XO will have the jitter that I need out to, say, 1 millisecond. So the 80K bangbang will have to take over there, without adding a lot of noise. With a better XO, the crossover time increases and the tradeoff is better.
--
John Larkin Highland Technology, Inc
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
A scheme like that would work if all I needed was a stable frequency. But I also want picosecond timing accuracy. Things like DACs, lowpass filters, and phase detectors will all have drift with time and temperature, and a picosecond is a cruel unit of measure.
An ECL bangbang phase detector is the only thing I can think of that has picosecond time stability, and it looks like it must work at 80 KHz. As Phil suggests, it could be the DC part of a compound loop.
--
John Larkin Highland Technology, Inc
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
That's unduly pessimistic. Before designing an instrument, I always calculate how good it _could_ be, from first principles where possible.
That way I can (a) select the best possible approach, and (b) know when it isn't there yet. I couldn't do my job without crunching a fair bit of math. My rule of thumb is that the final result gets within 1 dB of the theory most of the time, and within 3 dB almost always (i.e. unless I've made a math blunder or failed to think of some physical effect that turns out to be important).
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
hobbs at electrooptical dot net
http://electrooptical.net
Yes, understood. Offhand I don't see a simple way to make clean 10MHz from the 155.52MHz. I showed a clean, simple way to get the phase detector up from 80K to 640K instead. It's only 8x, but 8x is 8x.
Mike Perkin's method makes 10MHz with 15.552 quantized sine-steps per cycle, as you asked for.
That might be fine after filtering--I haven't done the math. My gut reaction to getting from 15.552 steps to ppb jitter just four octaves down is -- yowsa!
I've seen less steps used in generating RF waveforms with very good performance using the right filtering to remove the harmonics.
You won't even be too far along the sin(x)/x curve.
If the OP prefers more samples per cycle, then phase compare at 5MHz with over 31 sine-steps or start with 311.04MHz with over 31 sine-steps and divide by 2 to get 50% duty 155.52MHz clock. The variations are endless, each with its own advantage.
The principle is that you have more choice rather than being a slave to
80kHz and instead can choose the frequency you do the phase comparison at, and more choice over the pre and post phase comparator filters.
--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk
Sure, but you have to have an architecture to start with.
Sometimes staring at an equation does suggest an architecture.
You're more math-y than I am, so I tend to simulate more [1]. Electronic circuits are often sufficiently nonlinear that simulation is more useful than algebra. When you can trust it, of course.
And there's always soldering.
[1] or have a lackey do the math.
--
John Larkin Highland Technology, Inc
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
Normally a few possibilities, generated by some quality white-board time. (Preferably with some smart colleagues.)
It's really hard to get good minions nowadays. Beautiful Layout Hunchback just did her first thin-film RTD--22 mm square filled with serpentine traces, 2.5 mil lines and spaces, with a 28-mm pigtail (4-pin FFC for Kelvin connections). Made with 1/3 ounce copper, it turns out to be right around 100 ohms, and one of those places in Shenzhen is making us 40 of them for $100 shipped.
Sure is cheaper than buying them from Omega!
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
hobbs at electrooptical dot net
http://electrooptical.net
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