PLL tricks

I can see how a tank circuit could help with short term cycle to cycle jitter but not long term accuracy. John want ps accuracy which at 10MHz is 10ppm. Your drift would swamp that. Give a Q of 100, this implies your phase shift would be 100 x any component ppm drift.

I'm fairly sure that I understand that.

That's what he's presumably getting though he initially denied it.

They may, but the manufacturer doesn't guarantee their behaviour if you don't conform to the set-up and hold specifications, which does mean that what works with today's devices may not work after the manufacturer has tweaked the process.

John hopes that the output is "analog". It's certainly going to be filtered before it gets to the voltage drive that controls the phase (and - integrated - the frequency of the VXCO).

It wouldn't take much. The meta-stability window for ECLinPS is supposed to narrow.

He's used the same system - but clocked at 77MHz - to achieve a similar result with a different 155.52MHz clock, and the fact that he's not seen any metastability implies that what he's got does jiggle around enough.

It would be varactor-tuned, or you might be able to find one of the old YIG-tuned microwave oscillators, to lock the whole system back to the external 10MHz clock.

Without seeing the waveforms I have no idea.

What John is trying to do is make a clocked Sample/Hold using a flip-flop. Sampling the rising edge of the divided clock, rather than a true bang-gang phase detector.

As you say John would be dependant on a feature that isn't guaranteed by the manufacturer, where a small change in process might have consequences, such as introducing hysteresis.

I think a ps sample and hold circuit using a ring diode or similar would be be more reliable, where the rising edge of divided clock can be sampled to produce an analogue output dependant on relative phase. Gain and loop stability/accuracy could then be analysed.

I'd also want the whole circuit temperature stabilised!

In a classical frequency multiplier, such as an overdriven amplifier converting a sine wave to square wave and the LC is simply used to select the required harmonics. For a tripler, should take out the fundamental and 5th and higher order odd harmonics. the required attenuation determines the required Q.

A push pull doubler is nice, since it effectively removes the fundamental and the filtering only needs to remove the 4th and higher even harmonics, with low Q filtering.

The tank is not determining the frequency, the tank "locks" on to the input clock, exactly. Tuning errors only really effect the sub harmonic rejection. There is some some noise penalty, but not too significant.

I am just pointing out that tank multiplication gets lower noise than a PLL. You still have the issues of getting the correct input frequency.

Kevin Aylward

Ah... I should add... flat band noise with a multiplication of times 9. Multiplying up has an inherent theoretical noise increase of 20.log(mult ratio), so a times 9 is going to increase the basic oscillator phase noise by around 20dB, irrespective of any added noise of the processing. This means the oscillator noise floor needs better than -170dBc to get -150dBc out. This is actually quite difficult at a xtal osc frequency of 277Mhz.

At the moment, I have not assimilated what the graphs and data sheet in

Kevin Aylward

I was answering upsidedown's assertion that a high of 100 would be advantageous, where my immediate thought was it would be disastrous for long term stability.

Any analogue filtering will still have an effect around the frequency of interest, and so induce a phase dependent on temperature and to a lesser extent on ageing.

I don't feel maintaining waveform relationships to ps accuracy will be practical here using analogue filtering that is only an octave or two away from the fundamental.

Actually, I'm not concerned about that either. Metastability does not affect the performance of the bang-bang phase detector.

ECL flops don't catch fire when they go metastable; their prop delay just increases some. That wouldn't affect my phase detector; it arguably improves it slightly.

Circular definition: It means the the clock and data transition so closely in time that the flop goes metastable, teasing the setup/hold boundary within some number of femtoseconds.

There is no such thing as exact, only

I'm an engineer; I don't let philosophical arguments keep me from building and selling stuff.

In this case this window is *exactly* the

The ideal, noiseless bangbang PLL, with an integrator in the filter path, will have the phase detector flop alternate 1/0 as the phase alternates early/late, at successive sample shots. The dflop phase alternation then sets the loop jitter. DC plus 40 KHz ripple into the VCO.

But all real clocks have noise, so the PD flop output will in fact be a stream of random binary bits, at 80K bps, that servo to 50% duty cycle, with the rare metastability event. The binary noise stream gets processed by the loop filter into a DC level with some noise spectrum, and that goes into the VCO input of the 155 MHz VCXO.

Interesting loop. Sorta delta-sigma.

ECL tends to have extended prop delay on metastability events, maybe a plateau on the output edge, sometimes even a brief glitch in the wrong (non-ultimate) direction. Of course, there are different parts and families and manufacturers, but ECL in general doesn't do the many-cycle oscillation that TTL tended to do; probably a consequence of TTL being saturating logic and ECL being non-saturating. In my application, it wouldn't matter anyhow. If the clock edges are that well aligned, let it oscillate for a while.

John may be glossing over some aspects of what happens when ECL goes metastable and how often it might happen, but I'm not convinced it will be a problem when it does happen.

The normal output of the ECL FF will be a 1 or a 0 for 12.5 us at a time. If the FF goes metastable it will either be in the wrong state or will do some funny analog stuff like output an intermediate voltage or even oscillate. Since the output is being treated as analog and filtered, the worst case will be the wrong value for one sample period. I have to assume the filter and gain will result in a minimal impact from this. If the clock edges are so close the FF goes metastable which polarity is "wrong" anyway?

The worst I can see is that the circuit won't let the phase cross the boundary between positive and negative. Each time the phase delta gets close to zero and metastability gives a "wrong" polarity it "bounces" off the crossing and remains the same polarity. Not sure this is a problem either.

Even if his argument is just waving his arms, I think John is right in that metastability is not much of an issue.

Yup, 155 MHz needs to be thought about, but it is not at all unusual and is by no means a show stopper. Most likely the signal would need to be clocked into a FF in the IO block to minimize delay and if that isn't good enough it may require a PLL for the clock in the FPGA to offset the output delays.

There is also the issue of getting from CMOS to ECL, but I'm sure that isn't so hard to do with proper attention paid to the delays.

Am I? Gosh, I didn't know that.

I have observed setup/hold hysteresis in 10H-series ECL flops, on the order of a few ps, but I haven't measured it in the EclipsLite or EclipsPlus parts. It's not an easy measurement to set up.

Since I can expect several, maybe 10's of, ps of RMS jitter on my 10 MHz reference (or I can add it, if I want to) a little time hysteresis wouldn't affect my loop much.

It would need to be, if I used an analog s/h. The ECL flops, with differential data and clock inputs, are impressively stable with temperature. I've done this before, at 77 MHz sample rate, and got the entire instrument below 1 ps per degree C, with a bit of overall TC compensation.

That is an important point. Metastability will have a *major* impact on the *monotonicity* of the phase detector. If he wants to keep the two clocks to within 1 ps and the metastable window is 1 ps, he is doomed. Instead of being monotonic the phase detector may end up a random bit generator. This depends on the details of the window size and the behavior within that window. Normally metastable behavior is considered to be chaotic, not monotonic.

Ok, yes, that is a circular definition. The circuit will go metastable when the clock edges are close enough to cause metastability. Duh!

Where did you get the femtoseconds number? I thought elsewhere you said the metastable window was 1 ps??? This is a very important aspect of proper operation. If this window is large it will greatly increase the noise of the PD output even at very low frequencies below your filter cutoff.

Yes, I know, you build lots of stuff, you are just poor at discussing it in technical terms.

But the metastable may not be so rare. It pushes the VCXO in the opposite direction you want it to go.

"In general"? So it does oscillate. TTL doesn't *tend* to oscillate, but it will.

That's the scariest part of the problem. It will be a single-ended (BNC, coax) 10 MHz sine wave from a GPS-disciplined source. I need to bandpass filter it, to remove as much ground-loop-EMI crud as possible, and zero-cross detect it with a fast ECL comparator. So the BPF needs to have a super low prop delay temperature coefficient, which will no doubt be interesting. I assume we'll have an ambient temperature sensor on the PC board, and apply some sort of software tweak to the overall delay, to null out most of the delay tempco.

Last time I did this, I had a switchable loop filter. The supervising uP set it to wideband mode until it detected lock, then switched to narrowband mode to optimize jitter. That works if both the reference and the VCXO are pretty close to begin with.

I just read John's post where he said the reference clock will have 10's of ps jitter or that he can add it, so what is the point of a 1 ps accurate PD?

The problem with LCs is the temperature coefficient of delay. I'm in the time business here, not the frequency business.

I don't recall quantifying a metastability window. But I'd expect it to be pretty small for an 10EP52. It doesn't matter.

It does not. If the two clock edges are so close in time that the flop goes metastable, then it didn't matter whether the flop resolved to 1 or 0 on that shot. Metastability is the brass ring in this game.

ECL generally doesn't oscillate, but it wouldn't matter if it did. Each individual clocking event has a small influence on the input to the VCXO, and the resulting phase shift before the next clock.

You're unusually crabby today.