PLL tricks

.

But you can change the frequency by one resolution step from time to time, and reverse the phase creep - if you need to. Half a microHerz is rather mo re precise than John Larkin's 10MHz clock is ever going to be. With an atom ic clock system, you might want to manipulate the phase creep, but not here .

But you can write exactly the same number in rather fewer hexadecimal digit s, as long as you remember to include the trailing zeros as digits.

And if you knew your reference clock frequency that precisely.

No quite the same problem. John's desired output is a low jitter 155.52MHz clock, not an audio signal to be heard by a human being.

So John divides his 10MHz reference clock to 80kHz, counts transitions of h is nominally 155.52MHz clock and compares the sum with 1944. If the sum is

1945 the nominally 155.52MHz clock was running at 155.6MHz, and if 1943 at 155.44MHz and in either case some 6.4nsec of jitter have built up.

The problem with the digital domain is that it is slow and coarse.

The your VXCO had better have very good medium term stability, because you are going to have to integrate a lot of clock edges before you know enough to start twiddling the control voltage.

In other words, forget the 1psec jitter specification.

Really. One picosecond is a very well-defined interval. You seem to have de cided that having an edge creep a few psec away from it's nominal position doesn't matter if it a) happens slowly enough and b) will eventually creep back where it belongs.

You may be right, but that's not obvious from the way the problem has been stated.

--
Bill Sloman, Sydney

The DAC is built into the DDS. The low-pass filter doesn't have to be high- precision analog - it's just filtering out the spurs at 155.52MHz and its o dd multiples.

If your 10MHz reference oscillator is producing a decent sine wave (which s houldn't be difficult to arrange) and you use tolerably linear multiplying detector - my first thought would be an AD834, but it has been around for a while now - the residual spurs won't produce much in the way of DC output.

The comparator shouldn't have been there in the first place.

You will need an integrator (with a resistor in series with the integrating capacitor to turn the phase-detector output into a drive voltage for the V CXO, but that's all low-frequency stuff.

But where do you get the 24-bit number you want to multiply? You've got to count 100msec worth of 155.52MHz to get 2^24. that makes for a rather slow control loop.

Not anything like as Joergish as you like to think. Joerg is good at electr onics.

That he may be able to manage.

--
Bill Sloman, Sydney

No, it's a fractional multiply concept, and some fractions can be expressed exactly in some radixes but not in others.

Try expressing 1/5 as a binary fractional.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

I'm trying to fire the world's biggest laser.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

Nope. With binary, the DDS output frequency is an integer multiple of f_ref/2**N, whereas with BCD it's an integer multiple of f_ref/10**M. So you can write the same integer, but it won't produce the same output frequency.

Or, as is quite likely, other things are locked to that same reference, and need to interoperate.

The big problem with the DDS idea is the DAC+filter. In order to get rid of the jitter sidebands down to 1 ps, the analog stuff has to be accurate and stable to about

1 ps * 2 pi *155.2 MHz ~= 0.1%.

The bang-bang PLL is pretty good for the price.

I'm not sure it wouldn't work fine at 80 kHz, if John doesn't need the wide control bandwidth.

In a frequency multiplier, the RMS _phase_noise_ goes up by a factor of N, but that's because the period gets shorter and the _jitter_ stays the same (provided you get rid of the jitter of the dividers).

So John, how about that 80 kHz bang-bang thing with a picosecond ECL D-flop following each divider? Your loop bandwidth will be smaller, but the jitter should be fine.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net

Right. The dividers would be in an FPGA, but their outputs would be resynchronized to the two clocks, with ECL flipflops, to keep the jitter and drift down. Differential Eclips flops have sub-ps decision windows that have near zero temperature coefficients.

As far as the loop filter goes, the 155.52 VCXO will have some 1/f type jitter vs delay curve, which gets better as dollars are added. That curve doesn't matter at frequencies where the PLL asserts control. A slow loop filter forces me to buy a bigger, better VCXO that has less close-in phase noise. And it's hard to find a really good SC-cut OCXO oscillator at 155.52. The nice LVPECL VCXOs are tiny surface-mount things.

A really good soup-can sized SC-cut OCXO might have 1 ps of RMS jitter at 1 second delay. A cheap surface-mount XO might be 10 ns.

I can probably make it work at 80KHz, but I was hoping for some sneaky trick to get the phase detector frequency up.

The math of this - dividing to 80K, bangbang detector, loop filter, VCXO - is beyond me, so the best way to do it is to have a lackey breadboard a few versions. Even then it will be a challenge to test.

Last time I did a bangbang loop, I modeled the phase detector as a linear slope of voltage vs time error, with the width equal to some assumed jitter in both clocks, 20 ps or some such. That seemed to work.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

The DDS will have to have a high speed clock, e.g. 500 MHz or 1 GHz. The digital spurs have a different phase relationship with the sine wave output on different cycles, so they need to be filtered out to an accuracy of about

H ~ delta phi = 1 ps * 2 pi * 155.2 MHz = 0.1%.

That has to happen between 155.2 MHz and f_fast - 155.2 MHz, which for a

500 MHz f_fast is a pretty sharp filter. It can be done, but it doesn't happen by accident.

The drift will be horrible. 1 ps is 62 microradians at 10 MHz, so a drift of 0.006% of full scale eats up the whole timing margin. It's dramatically harder at 80 kHz, because the resulting jitter goes as N, unlike the bang-bang loop.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net

It's still the same number, even if it won't generate the same frequency.

Essentially, using decimal numbers is a bad idea. It uses more silicon area to achieve much the same result.

Obviously.

That's a problem of clock distribution - which is interesting in it's own r ight, but not what's been being talked about here.

Rubbish. The DAC is just producing a tolerable approximation to a sine wave , and the imperfections should get largely get filtered out before the DDS output gets into the phase detector. Most of the side-band products get fil tered after the detector anyway, and any DC that's left is a constant (and small) phase offset, not a frequency offset (if you do it anything like rig ht).

It's a can of worms. Any noise on the rails can creep on and shift the swit ching point. A product phase detector is a lot more forgiving.

If he went out and bought a decent VXCO, which was an off-the-shelf item 20 years ago, and ON-Semiconductor now seems to offer as an SMD component, he could live with a really slow and heavily filtered phase detector running at 80kHz, but either a DDS or a fractional-N divider could be made to work at 10MHz and would give much faster feedback.

Resynchronising TTL outputs with an ECL bistable would work fine. The last time I did that was with a 200MHz clock and the delay tolerance through the TTL was more than 5nsec, so we got the user to pick the one of four possib le edges that was furthest away from the actual TTL transition and select i t with a pair of switches.

Worked fine until some half-witted graduate student hooked up the balanced clock drives wrong way round, which moved the active edge from the best pla ce to the worst place ...

It was the usual tidying up ten years after the original design kind of job , so it was all a bit rough.

--
Bill Sloman, Sydney

1/101 (binary).

When you can pick a fraction of 2^48 you can usually express what you want more accurately than you can measure it or specify it.

--
Bill Sloman, Sydney

Quit pontificating and do the math. It's as I said. Phase error due to additive signals goes as the spur amplitude divided by the maximum phase slope of the desired signal. 'Tain't rocket science.

John has shipping products with 1-ps jitter. I have a digital delay box of his that has 5 ps of jitter, which is about 35 dB better than the SRS box I used to have. So rather than preening yourself, you might listen and learn.

John was asking for a smart idea, in order to save money.

Money is good. I like money, John likes money, and so do you. I'd much rather deploy a smart idea than spend extra money. So would you, provided the idea was yours.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net

Not in this context.

If you want something - as John does - to let you compare your 155.52MHZ VC O with a good quality 10MHz reference oscillator, the DDS is driven directl y from the 155.52MHz oscillator John wants to stabilise and lock to the 10M Hz reference oscillator.

A fractional-N divider would be cheaper, but messier.

You can buy DDS with a built-in frequency multiplier.

has an internal VCO that runs between 2.4 and 2.5 GHz which could be locked to a multiple of 10MHz reference, but if you'd bought that you'd use it to generate the 155.52MHz output directly, and leave all the phase detection etc to the insides of the Analog Devices chip.

Only if you were silly enough to use an edge sensitive phase detector. Prod uct phase detectors are lot more tolerant and forgiving.

Happily, it doesn't need to be done that well, or anything like that well.

What drift?

The whole point of a second order phase locked loop with an integrator driv ing the VCO is that the waveform coming out of the divider from the VCO is forced into a fixed phase relationship with the waveform coming out of the reference.

High frequency harmonic content on the DDS output would mean that the fixed phase relationship wouldn't be quite where it would be for a pure sine wav e, but it won't move around unless the harmonic content changes, which it w on't.

Floyd M. Gardner is a full bottle on the subject. The loop filter I've got in mind (and have used from time to time) is figure 6.1 (b) in his book.

--
Bill Sloman, Sydney

I'm only going to build 8 of the boxes in question, so money isn't really a big deal, except for the Joergian sporting aspects. I thought the PLL math was interesting, and a discussion group does need stuff to discuss. Talking about problems with other people helps me to think, too.

I'm not an RF sort of guy - sine waves are BORING - and some people here are, so it's interesting to get some fresh ideas.

It occurs to me that there's a lot of similarity between a noiseless bang-bang PLL and a duty-cycle integrating ADC, and a lot of similarity between a noisy bangbang and a delta-sigma ADC.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

Sure. Helps in keeping out of ruts. And sine waves are only boring if you have a short attention span. ;)

If you want to use a bang-bang loop with a single phase detector, and avoid analogue precision (even filters), ISTM you're pretty much stuck with 80 kHz, or the equivalent (e.g. synthesizing 1.5552 GHz and dividing down). Any mixing or frequency-offset scheme is going to require filtering.

One possibility is to use local feedback: run a quiet-but-perhaps drifty offset PLL with a nice wide bandwidth to make your 155.52 MHz, and wrap it in a bang-bang loop at 80 kHz to take out the drift, perhaps by putting a varactor phase shifter in the 10 MHz going to the analogue loop.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net

Not in a product detector. And the phase error is static and should be smal l. The higher frequency harmonics cancel out in proportion to the harmonic number when you integrate over a whole cycle.

I was doing as well twenty years ago, when it was all a bit more difficult. It was Gigabit Logic's GaAs parts back then - ECLinPS (which I've used) is easier to use and ECLinPS+ is now a bit faster.

The fact that John can make his stuff work is impressive - lots of people c an't - but I did as well quite a while earlier, and so far I'm not hearing anything that anybody ought to take too seriously.

He got several, and didn't seem to take any of them seriously.

Several people have pointed out that fractional-N would work at 10MHz. I'd be happier using it with a product phase detector, but the jitter from the moving fractional-N edges can get filtered out before it gets anywhere near the VCO drive. DDS is cuter, but DDS chips are expensive - the AD9102 cost s $30.

The chemically thinned 155.52MHz crystal for a VCXO wouldn't be all that ch eap, but if ON-Semiconductor is putting them into SMD packages the process for making them must be pretty thoroughly automated.

--
Bill Sloman, Sydney

I suspect that you've done the math you usually do, which is for random noi se at different frequencies.

In this situation, the harmonic content is pretty much deterministic, and t he same from one cycle to the next. As I said, it can create a static phase shift, but no noise or drift. In the fractional-N at 10MHz system, success ive cycles will have different phase shifts - within a 6.4nsec window - but that will repeat exactly every 12.5usec, and most of it will cancel out a lot more rapidly.

--
Bill Sloman, Sydney

Wrong. Do the math. If the jitter were the same from cycle to cycle, you wouldn't need a DDS register any wider than your DAC.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net

I don't agree that, in general, that the noise profile of a fractional-n is repetitive. A fractional-n will realistically, today, pretty much be a multi-order delta-sigma configuration, probably... delta-sigma systems are chaotic . i.e. pretty much random. Indeed, the task is to make it as random as possible. I haven't followed this tread in detail so not sure what noise to which is being referred to.

Somewhat interestingly, when John Wells of Marconi invented the delta-sigma approach to synthesisers, it don't seem that the bigger picture of where that approach sat was known. To wit, recognising the binomial expansion of (1-z)^n to get the best approximating delay co-efficients and its relation to ADC.

Kevin Aylward

- SuperSpice

This entire thread... wow... just, wow.

Look up variable-modulus DDSes. They are cool.

-- john, KE5FX

No Phil, you're mistaken. John's a mechanic / fiddler who only gets things right accidentally. NOOTTTTT! :-)

I'm about to go for a jog, but how about some analog ideas?

e.g., if the PLL error signal is messy, add in a jitter-compensating signal.

e.g., do fractional division with an integer number of clocks plus a varying analog ramp delay. That would let you keep a much higher reference frequency.

Even a ramp with horrible resolution is way less jittery than alternating the divider modulii.

Cheers, James Arthur