PLL tricks

To fire things on time. My PLL can clean up jitter on the 10 MHz reference.

On a sunny day (Sun, 14 Sep 2014 12:09:47 -0700) it happened John Larkin wrote in :

If you have frequency lock, then an analog delay line (varicaps + L) can be used to 'reposition' the edge, if it is the edge that must be positioned relative to some other edge... A controlled delay line that is. This reminds me of the sixties Ampex video recorders, to give some loops over loops: Rotating video head at 250 revolutions per second, video (color, chroma) needs to be within say 12 nS. So the way this was done is

Anyways 50 years old technology. But it had a reference, everything in the studio is locked to it.

You can have a noisy reference, and make an almost jitter free RF signal, but you cannot have a jitter free RF signal if you align with the edges of a noisy reference.

So question is what do you want? For a sine wave reference as you say I see plenty of 'alignment' problems [1], So it seems then that you just want the average frequency and that jitter free. But of some laser has to trigger on the 'edge' of the reference, the delay line method comes back into play.

Well just a bit of old days and philosophy. Especially as I am watching a startrek movie were Kirk just got sucked out into space.

How come the Enterprise, no matter how badly it was shot up, never lost pressurization and never lost its artificial gravity generator?

And why did they always beam into derelict spaceships and alien planets that had breathable atmospheres and Earth-level gravity?

Why were no babies ever born on the Enterprise? Why did nobody ever bleed or vomit? Did they have unisex rest rooms? Did they have bathtubs? Where were the trash cans? Were snacks not allowed on the bridge?

Resynchronizing to the 10 MHz clock after the phase detector would fix it if it were a problem, anyway. That won't add any significant phase delay in an 80-kHz comparison.

Cheers

Phil Hobbs

I think that's a problem calling for measurement, rather than speculation. As arguments go, saying that A is "considered" B is about as weak as it gets.

Interesting thread, anyway.

Cheers

Phil Hobbs

Acquisition aids are a separate problem. I was talking about

Cheers

Phil Hobbs

I agree that just hanging the PD D-flop on some noisy digital rail isn't a terrific idea. OTOH I sort of suspect that there's not that much ECL on the board, and of course FPGAs and such need lots of independently regulated rails anyway. It's not especially difficult to reduce the externally-coupled noise on a rails to well below 1 nV/sqrt(Hz), regardless of what the input supply looks like. That's probably well below the input-referred noise of the D-flop.

The rail might bounce a bit due to load fluctuations, but one of the great virtues of ECL is that there's very little data-dependence of supply current.

Cheers

Phil Hobbs

But not the jitter. The reason the phase noise goes up is that the jitter stays more or less the same, but the period goes down by a factor N, so the phase fluctuations increase by N times.

Cheers

Phil Hobbs

Yup.

Cheers

Phil Hobbs

In the words of Rudyard Kipling, "Not so, but far otherwise." For a single section the phase shift across the width of the resonance is on the order of 1 radian, so in terms of phase, a filter with a Q of 100 magnifies the component tempcos by roughly 100 times. A time shift of 1 ps is about a milliradian at 155 MHz. Typical inductor tempcos of +100 ppm/C will give you a phase shift of something like

dPhi/dT ~ Q * dL/dT

or 0.01 radian/K, i.e. 10 ps/K.

Cheers

Phil Hobbs

Hardly.

And you are the same as always... thick. You say it doesn't "generally" oscillate which means it *does* oscillate. The qualifier is a waffle word. The fact that you run the output through a filter doesn't mean it won't oscillate.

Right. ECL is remarkably indifferent to supply voltage, or even to the voltage applied to external pulldown resistors. But of course I'll have good supplies; that's easy.

Since you are mentioning really clean supplies: I have built a preamp to verify the noise on supplies and Vtune lines:

and used it to measure the noise of batteries, simply because they are probably the hardest test objects.

It's not yet accesible from the rest of the website, you must know the exact address since I'm not yet happy with the results. I see much more 1/f noise than F.Walls from NIST, and partly 30 dB/decade.

I have used an old Avantek wideband amplifier with 57 dB gain and mixed down the noise @100 MHz with a signal generator, ring mixer & low pass to AF, and it was as flat as could be down to 0.1 Hz. So if it's flat, the system shows it as flat. wierd.

regards, Gerhard

Nice. If you make two amplifiers, take the cross-spectrum of their outputs, and average for awhile, you can get rid of the amplifier voltage noise pretty well. (The current noise adds, of course.)

Cheers

Phil Hobbs

Why do you not understand that the jitter and delay of the divided clock is not an issue? It is not being used to clock anything. It is only being used to isolate the actual clock edges by enabling the FF. It only has to meet setup and hold times.

BTW, the FF has to be clocked by the same clock that is being divided down. Otherwise you get 1 full clock cycle of jitter in the enable when you sync it to the other clock.

I was thinking of doing something like that with a bunch of jfets. BF862's have about 800 pV/rthz voltage noise and very low current noise. Less propensity to rectify RF, too.

Wish I had a use for it!

A very vague explanation. You are using a 1 ps accurate rifle to hit a target that is moving around by 10's of ps. Then you want to determine where the target is by watching the rifle.

I think you can have a rifle that is not so good as 1 ps and still get the same result. It all runs through the same filter.

Am 15.09.2014 um 01:00 schrieb John Larkin:

Someone has done this with 32 BF862. Each group of 4 needs a ferrite bead against. osc. I have once used 2 * 8 2SK-something in front of a ad797. That was quite unstable: 1/f of the FETs, thermal drift, not much supply suppression because of balance. FETs are all individuals.

With the averaged op amps, the input pairs are at least on the same chip.

cheers, Gerhard

I've enjoyed this, and understood maybe half of it. (I think this has already been suggested) Could you divide by N on negative edges, and then alternate on the positive edges between, M and L. With three numbers maybe there is some higher common factor?

George H.

elative stability misses the point that dividing the 155.52MHz down to 80kH z introduces more than a 1psec of phase shift, as does dividing 10MHz down to 80kHz.

ctor, ignores all of that, and the delays through the filtering after the p hase detector which is absolutely necessary if the noise on the phase detec tor output isn't going to produce phase noise on the sine wave coming out o f the VCXO.