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PLL tricks

If I hypothetically had a 10 MHz reference and wanted to lock a 155.52 MHz VCXO to it, the obvious way would be to divide both down to 80 KHz (the GCD) and drive a phase detector back into the VCXO. But that's a pretty low frequency to run the PD at; to get picosecond stability, an ordinary analog phase detector would need better than 1 PPM analog accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but

80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but that sounds jitterey to me, and it looks like I can't hit the exact frequency ratio anyhow.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin
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Investigate how "dual-modulus" pre-scalers allow a higher reference frequency. ...Jim Thompson

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Reply to
Jim Thompson

It's only jittery if you don't filter the DDS output carefully. The phase d elay through the the filter complicates the dynamics of your phase-locked l oop, but FloyD M. Gardener's "Phase-Lock Techniques" (ISBN 0-471-04294-3) w alks you through that - his chapter 7 "Optimisation of Loop Performance" is all about that.

The latest copy of LT's Journal of Analog Innovation talks about "fractiona l-N PLLs". It's touting their LTC6948 integrated circuit, and the write-up doesn't tell you much about realising a fractional-N divider.

Dividing by 155 for four cycles and and by 156 for the next cycle gets your 155.2MHz down to 1MHz (on average). Dividing by 15 eight or nine times in succession and by 16 on the nineth or tenth time - you need to run an accum ulator to tell you which - does the same job at 10MHz.

As you say, it's jittery, so you have to filter the filter the high frequen cy components out of the phase-detector output (which may need a sharp notc h) before you feed it back to the VCO.

A DDS includes the same kind of accumulator, but uses a DAC to smooth out a lot of the digital lumpiness, so it has to be a better way to go, though y ou still need to filter out the square step edges in the DAC's "staircase" approximation to the desired sine wave

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Bill Sloman, Sydney
Reply to
Bill Sloman

Use a VCOCXO, a very stable oscillator and a long time constant in the loop.

GPSDOs use 1-pps for the loop.

Reply to
Tom Miller

I'm reading my PLL books (Brennan, Wolaver) and it's complex. Fractional-N type techniques need analog phase detectors, which will cause me to have analog-based phase errors, and they introduce messy sidebands, namely jitter in my world.

What I don't need is tunability: my frequencies are what they are. So maybe there's some math trick somewhere.

I don't know if I can buy a good 777.60 MHz VCO. If I could, I could run the phase detector at 400KHz, and divide the 777.60 by 5 to get

155.52. Or VCO at 1.5552 GHz, PD at 800K, and divide by 10. 
--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Probably so. I'd need to find a really good 155.52 VCOCXO. An SC-cut rock would be best, but I don't know if they run that high.

I can do adaptive acquire/lock tricks, so the operating loop bandwidth can be whatever works best. Tracking mode, loop bandwidth could be 100 Hz, or less.

Brute force, no math tricks.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

For integer division ratios, you're still limited to the GCD of the RF and reference frequencies--10 MHz = 125*80 kHz, and 155.2 MHz = 194*80 kHz. 125 and 195 are of course relatively prime.

One approach that we've discussed here in the last year or two is to use pulse swallowing (as in a dual modulus) but not every cycle of the comparison frequency. I did this over 30 years ago using CD4527 rate multipliers, which works fine but does exhibit birdies at some division ratios, since the rate multiplier has short-period regularities in its pulse pattern.

As somebody here suggested awhile back, in principle you can use noise shaping to move most of the deterministic jitter out of the loop bandwidth. I've never done it, but it would be an interesting approach.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Sideband locking is a reasonable approach. Make 150 MHz, mix down to

5.52, and lock that 1:1 with a DDS. If you use a VCXO, there's no way it'll lock up on the wrong sideband.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

ur 155.2MHz down to 1MHz (on average).

That would work (I think, but then I thought that the next sentence was rig ht too).

r tenth time - you need to run an accumulator to tell you which - does the same job at 10MHz.

Actually you have to alternately divide by 15 and by 16 most of the time, a nd by sixteen an extra time from time to time - to get 155.2MHz down to 10 MHz.

155.2MHz is a period of 6.4433nsec (almost) and you need 15.52 of those per iods to add up to 100nsec. As John says you can make it exact over 12.5usec - 1940 cycles - which is 65 cycles of divide by 16 and 60 cycles of divide by 15, 125 in all, so the extra divide by 16 cycles show up about once per 25 cycles of division. That's about 33nsec of jitter on every transition o f the nominally 10MHz output that you are feeding back into the VCO, which is going to be a tolerably high level component that you are going to have to explicitly filter out.

This is why the DDS is better - the output DAC on the DDS smooths that out a lot.

You could write a list of the 125 more or less alternating divider numbers (either 16 or 15) into memory and just cycle through them continuously, but an accumulator and a digital magnitude comparator would use up less cells in a programmable logic device.

--
 Bill Sloman, Sydney
Reply to
Bill Sloman

You can get chemically etched quartz crystals with fundamental frequencies up to 500MHz. I was looking at one back in 1996. ON Semiconductor seem to have been able to find them in October, 2009.

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and the VCO version in December 2010

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NBVSPA015/D in the NBVSPA015 Series on the data sheet.

And not much idea of what you could buy to do the job.

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Bill Sloman, Sydney
Reply to
Bill Sloman

eriods to add up to 100nsec. As John says you can make it exact over 12.5us ec - 1940 cycles - which is 65 cycles of divide by 16 and 60 cycles of divi de by 15, 125 in all, so the extra divide by 16 cycles show up about once p er 25 cycles of division. That's about 33nsec of jitter on every transition of the

Not my day. I meant 3.2nsec of jitter - though the edge mores back and fort h across the 6.4433 nsec window as the divider adjusts up and down.

ing to be a tolerably high level component that you might explicitly filter out, by putting a notch in the filter.

-- Bill Sloman, Sydney

Reply to
Bill Sloman

I need to run at 155.52 MHz (OC3 telecom rate) which is 1944 * 80K. But the GCD is still 80K.

The edges of 10M and 155.52M coincide every 12.5 us. At that instant, I can do an early/late test (with an ECL D-flop) with almost infinite gain and picosecond stability. In fact, I don't even need to divide one of them.

Any pulse swallower or fractional-N thing will have one set of edges hitting early/late around the other, and depend on the loop filter to average things out. That will require analog precision, lots of analog precision to get picosecond precision.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Am 10.09.2014 um 01:54 schrieb John Larkin:

Dividing EXACTLY with a DDS can be surprisingly hard, one could find that one is always off by 2e-32 or 2e-48 or whatever but one is never exactly on the spot, never really synchronous.

Once, there was a BCD coded DDS from Stanford IIRC that could get it exact for easy-to-write decimal numbers.

Today one could put it into an FPGA. A BCD based adder is easy. I have put a VHDL-only sine table on opencores.org that should also be easy to modify.

regards, Gerhard

Reply to
Gerhard Hoffmann

It's clunky, but no tricks required:

increase 10 MHz by 3^4 yielding 810 MHz

Divide 810 MHz by 5^3 yielding 6.48 MHz

increase 6.48 MHz by 2^3 * 3 yielding 155.52 MHz

The prime factors for these odd-sounding frequencies are surprisingly small.

ChesterW

Reply to
ChesterW

I guess you could probably use an ADF4351 frac-N synth with 10MHz comparison frequency, to synthesise 2.48832GHz and then use the internal divide by 32 to get back to 155.52MHz. They claim 0.3ps rms jitter.

If you wanted to improve the jitter a bit further, you could take the

2.48832GHz from the first frac-N PLL and then use an integer-N PLL to lock a really quiet 155.52MHz VCXO to that. I would suggest using the "reference" and "feedback" dividers of this integer-N PLL for the opposite of their usual intended purposes, as that would suit the frequeicies involved. Normally you can swap the charge pump polarity in software if needed.

If you really don't want to use a frac-N synth anywhere, you could e.g. synthesize 240MHz from 10MHz with a first integer-N PLL, with a 10MHz comparison frequency, then synthesize 155.52MHz from the 240MHz using another integer-N synth with a 1.92MHz comparison frequency.

Chris

Reply to
Chris Jones

I used my fraction-N divider generator to generate a 155.52 MHz to 10 MHz fractional-N divider circuit.

It said that the jitter had a fundamental frequency of 80kHz and an amplitude of 6.4ns p-p. That makes sense, as 80kHz is the GCD (as you noted).

I then ran it through another program of mine that shows the spectral content of the jitter. I was surprised to find that there was no 80kHz component. It seems the jitter only has components at 160kHz and harmonics of 160kHz. The strongest component is at 320kHz.

How good is the 155.52MHz VCXO? If you can get the PLL loop bandwidth low enough, the 160kHz (etc.) spurs won't be a problem.

That's only a problem with a naive DDS design.

Regards, Allan

Reply to
Allan Herriman

Getting the fast jitter components that low isn't too hard, if you start with a VCXO, I wouldn't think. The wandering around due to analogue offset drift is the primary problem, I gather?

I've only ever used flipflops as mixers once. They were 74S112s, iirc, because the J-Ks toggled faster than the Ds. The metastability was _not_ pretty--on a spectrum analyzer, the 909 kHz IF looked like one of those old bubbler water fountains.

If you're using a bang/bang phase detector, how do you avoid horrible metastability? (I normally think of an early/late gate as a digital PLL function rather than a real phase detector.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Last one I did at 155.52, I used an EclipsLite d-flop. ECL has nicer metastability behavior than old TTL. 74LS was the worst, as I recall.

In a bang-bang phase detector, if it goes metastable for a few hundred ps, who cares? The 1/0 decision must not matter if the edges are that close in time.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Right. One rounding bit out of 48, or even 64, would give me a slow phase creep.

Yeah, decimal might work.

That is interesting. We might look into a decimal DDS.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

The divisor for 80 KHz mixing are 125 and 1944.

125 = 5 * 5 * 5

1944 = 2 * 2 * 2 * 3 * 3 * 3 * 3 * 3

so there are things that can be done.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

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