Right. What Sloman described isn't a DDS, it's an elaborate, expensive, drifty, noisy divide-by-1944, and the phase comparison would still be at 80 KHz.
So, why not just divide by 1944?
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Cool. 523 posts to this thread so far.
This might work:
It still does the phase compare at 80 KHz, probably a mathematical necessity in my situation. But the phase detector gain is way higher than a classical 2-pi phase detector... 1944 times as high, to be exact. Picoseconds of phase error now become parts-per-thousand turf, not parts per million.
The advantage over a bangbang detector is that the phase detector output is linear on phase error, so the loop could be analyzed as such, and will be far less noisy.
That 6 ns series gate, stable to around 0.1%, is non-trivial.
Ooh, that suggests a phase ADC, in a digital loop. Or maybe a multbit bang-bang phase detector. Maybe later.
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Wrong - on several counts. The main point is that that with either fractional-n or DDS you derive a nominally 10MHz waveform from your
155.52MHz VCXO and do the phase comparison at 10MHz rather than 80kHz.In neither case is the derived 10MHz waveform perfectly regular - the DDS approach gives you something much closer to perfection than the fractional-n approach and you pretty much have to use a product-type phase detector, carefully analog-designed to give you a tolerably linear phase-offset to voltage-out relationship, so that the residual imperfections average out over the 80kHz cycle over which they repeat.
The DDS approach does involve more propagation delay in the path from the 155.52MHz clock signal to the derived 10MHz waveform. It may strike you as an elaborate approach, but I do seem to have worked with more complicated systems than you, and it doesn't strike me as all that complicated.
It needn't be all that drifty or noisy. The fractional-n approach is simpler and involves smaller propagation delays, and while the individual edges on the derived 10MHz do gad around more - up to 6.4nsec
- the deviations aren't random noise but systematic and entirely predictable excursions.
For the reason you set out when you opened this thread - getting information on the relative phase of the two waveforms at 80kHz rather than 10MHz makes the system more susceptible to random noise in the phase-detector. Using a thoroughly non-linear bang-bang phase detector to do it makes the situation somewhat worse.
-- Bill Sloman, Sydney
On a sunny day (Wed, 24 Sep 2014 08:01:46 -0700) it happened John Larkin wrote in :
Yes John, I invented that back in 1984
I suspect someone else invented it before either of us. I invented the bang-bang phase detector ca 1972, ditto.
The trick would be to make that series switch work with roughly 0.1% precision, given a 6 ns gate.
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Phase digitizers are fun. I did one as a grad student, back around
1986--it ran at 60 MHz, 50k samples/s, and was good to 13 bits over a cycle. It used an old-fashioned SAR chip plus DAC plus varactor phase shifter, with a Mini Circuits RPD-1 phase detector. (It was one of the two instruments papers I ever published.) (*) 1 LSB of that digitizer was about 2 picoseconds--I learned the horrible truth about picosecond stability and bending coax cables. ;)The stability of just the digitizer and its associated calibrator (which was several times more complicated) was about +- 0.05 degrees over a few hours, which is about +- 2 ps.
Cheers
Phil Hobbs
Hobbs, P. C. D., "High?performance amplitude and phase digitizers at 60 MHz", Rev. Sci. Instrum. 58, 1518 (1987)
I don't think I have a copy any place, or I'd post a link.
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Or at least make its imprecision symmetrical, e.g. with a 2-diode series clipper.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Adding 847 and subtracting 177 are the same modulo 1024. The number of FFs is not the issue. The number of adders and multiplexers and where they are placed is the issue. If this is coded in a sloppy manner it can produce more logic than is needed.
-- Rick
Uh, it's not dividing by 1944... It is producing 10 MHz, not 80 kHz. Did you actually read any of this?
-- Rick
If I have 100,000 mosquitos, can I use them to charge my phone?
Sure, do you have the appropriate adapter cable? I bet you can find one on AliExpress...
-- Rick
If I shaped the rising edge of the 10 MHz square wave, and digitized that with a wideband ADC triggered at 80 KHz, I'd get an ADC code that was about linear on phase error with full-span of 50 ps or some such. Even 8 bits would get the LSB into the sub-ps range. Then do a digital PID loop driving a DAC into the VCO input. I do something vaguely similar in my DDGs.
Even more radical, digitize the 10 MHz sine wave at 155.52 MHz sample rate and do a monstrous amount of math.
Multibit bang-bang would use several flops staggered in time to make a thermometer code of phase shift. That would improve my loop noise a little.
Single flop bang-bang is looking pretty good!
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
That would be a huge waste of resources. Use the fractional-n approach to d igitise at 20MHz, using the nearest 155.52MHz edge after the rising and fal ling 10MHz edges. You'll be able to predict how much later the digitisation ought to be happening, and interpret the ADC output as an exact - linear - time delay correction. You'd have to shape the 10MHz edges enough to give you something worth digitising up to 6.43nsec - probably actually closer to 12.86nsec - after the start of the 10MHz edge transition.
That does insert something like 7nsec of analog delay/time constant into yo ur sampling path, and you'd have to do careful analog design to keep the te mperature drift on that below a picosecond or so.
That does imply a precise and stable tapped delay line for the multiple D-t ype flip-flops to sample - all at once - at 80kHz. If you made the delay li ne longer than 6.44 nsec, you could use fractional-n division to let it sam ple at 10MHz but you'd then have to take out the predictable - up to 6.44ns ec - excursions - on the non-coincident edges .
Self-delusion.
-- Bill Sloman, Sydney
Am 25.09.2014 um 04:40 schrieb John Larkin:
I had proposed that already for the almost all digital solution. The filter after the 10 MHz digitizer could be a FIR and you get zero crossings given by 2 samples 7 ns apart, each with say 16 bits. The monstrous math would be just interpolation between 2 samples, maybe 3 samples if you want to remove corner cases.
The aperture jitter of a 200 MHz 16 bit dac is abt. 50 fs just for bragging rights 16/200.
You could use every rising 10 MHz edge, and, if you want, every falling, too, The statistics of rising vs. falling would indicate if you filter enough or if the 10MHz ref has a stable duty cycle.
There also would be no DAC after the DDS sine table, just one after the phase detector (aka 16*16 multiplier) + interpolator that outputs >= 16 bit values for the VCO tuning voltage with
10, 20 or 155 MHz or submultiples thereof pre-averaged by a FIR.None of these filters would drift in any way.
That is just a corner in a small Spartan-6 or newer.
regards, Gerhard
p.s. do you really use 10K FFs or 100K series that has temp. compensation?
Which 16-bit 200MHz ADC?
No, but to give ADC something meaningful to sample you'd have to low-pass f ilter the 10MHz edges before you fed them into the ADC, probably with somet hing like a 7nsec single-pole Converting the edges into linear ramps would be nice, but tricky (particularly if you wanted a rock-solid time constant for eventual sub-picosecond accuracy).
For the computational part.
-- Bill Sloman, Sydney
On a sunny day (Wed, 24 Sep 2014 10:32:41 -0700) it happened John Larkin wrote in :
Yes, many of us probably invented the wheel at some time.
The reason I came up with this was quite different. In those old days floppies were fully of dropouts. That caused missing pulses, driving the common phase detectors way to a lower frequency. This circuit opens the sample gate only when a signal is present, else it will keep running at its last frequency. It worked so well that you could break a floppy with your fingers to a slow speed and would still read the data correctly. The 'gain' (proportional) is in the width of the pulse that opens the switch. So in theory at least, you can, after frequency lock, change that pulse width to change the gain. Was not needed in this circuit.
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Now, that was hard!
That would be a real problem with nearly 16 times oversampling. For some.
Gerhard
He's probably using MC100EP parts - 10K and 100K was around thirty years ago, and ECLinPS is a whole lot quicker. The distinction between 10 and
100 series ECL from Motorola is that 100 series parts have a temperature compensated logic levels and threshold (as you probably know - as I should have deduced from your last sentence after reading it very carefully)The logic levels specifications for the 10EP16VA and 100EP16VA parts tell the story. I know John's fond of the ECLinPS parts - he tells us so from time to time. I like the original 100EL parts when I could first get my hands on them, back around 1995. There was publicity for them - but no parts - back around 1990 when I really could have used them, but had to settle for Gigabit Logic's GaAs parts.
-- Bill Sloman, Sydney
:
But it doesn't answer my question. Are you prepared to guarantee that every
16-bit 200mHz ADC has the same - nominally 50fs - aperture jitter?I'd feel more comfortable with an explicit example.
ss filter the 10MHz edges before you fed them into the ADC, probably with s omething like a 7nsec single-pole. Converting the edges into linear ramps w ould be nice, but tricky (particularly if you wanted a rock-solid time cons tant for eventual sub-picosecond accuracy).
16-times over-sampling doesn't help much if all the samples taken are eithe r high or low.This is where you have to find a way of dithering the signal you measure in order to get a least one sample that is neither high nor low.
Low-pass filtering the 10MHz edge to convert it into something that spends at least 6.43nsec moving from high to low means that your ADC sampling at 1
55.52MHz will have some idea when one edge started moving. Only one in seve n or eight will offer any timing information, and you'll have to check the previous sample to find out whether the ramp started off from high or low.Once you've got some idea of what's going on, you'll know which edges are g oing to be worth sampling, which may save you some processing.
Some A/D converters get shirty about digitising very rapidly moving edges - another reason for being explicit about the device you have in mind.
-- Bill Sloman, Sydney
Am 25.09.2014 um 10:55 schrieb Bill Sloman:
For me, it's enough that AD, LT, TI and others guarantee it.
You can calculate yourself what worst case aperture jitter is required for 200MHz/16 bit. Take a full scale sine wave at fNyquist, consider the steepest part in the middle: how much risetime does it take to change the reading from 0 to 1 on a +-32K scale?
If you cannot fix your sample point better in time than that, you have no real 16 bit / 200 MHz DAC.
Most fast 16 bit ADCs spec sth. like 65 fs, and there are other errors like noise, drift etc. No one expects full 16 bit accuracy.
Nobody would ever want to dither that. One gets every 10 MHz transition and the digital low/high pass makes a perfect sine from it, no offset, harmonics, noise, just remove the mirror at 145, 165, 300 MHz with an analog filter.
There won't be much to do. It does not matter if the 10MHz is a sine or square wave. Time labs prefer sines because one does not have to care about reflections of the harmonics.
After filtering, you have a 16 bit digital sine wave that you can multiply with a 16 bit digital sine wave from the DDS in one of these DSP-48 blocks at a 155 Mwords/s rate.
Low pass filter with a FIR or CIC and output it to dac with your choice of sample rate and resolution. A slow 20 bit would be cheapest, probably.
Gerhard
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