Packaged D-flops rarely come with clock enable pins in my universe. John specifically said that you needed to drive the DFF differentially to get the good jitter numbers, so despite having CLK and /CLK pins, there's nothing to use as a clock enable.
The usual method for resynchronizing is to put the divider output into D and clock it with the undivided signal.
Doing that would break the PLL, so I'm obviously not proposing anything so idiotic.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
Well, John did not say what exactly he's trying to fire, but it looks like he means the "rifle" with the 500 TW. That's a highly distributed "rifle" with 192 "chambers" being fired synchronously. John's probably building the "mechanism" responsible for the action of each "pin".
(John, correct me if I'm wrong ...)
The one thing that strikes me as really odd, is that they want the thing to be synchronized to a 10MHz signal over coax lines. The use of a higher frequency and fiber optics would likely provide a much better distribution of the timing signal.
Maybe John should consider running his own ovenized "master oscillator" at a suitable (higher) frequency and PLLing it to the incoming 10 MHz with a very long time constant (some people on the well-known Time Nuts mailing list temperature-stabilize the ovens of their own GPSDOs to millikelvins and then run the PLLs with filter time constants on the order of hours or even days in order to keep ADEV as low as they can, but then they only have a PPS signal to start from). Having 10 MHz to start from is obviously much better than 1 PPS, so there's no need for hours or days of PLL stabilization time, but still, using a more short term stable (translate: less jittery) internal reference is probably something to consider, before starting to synthesize the 155 MHz.
Regards Dimitrij
How would that break the PLL? The reference clock is sampled by the D input clocked by the VCXO clock. The divided signal has to be an enable on the FF or it won't work because of the inherent delays in generating the divided signal.
If you reclock the divided signal there will be tons of delay in even an ECL FF.
-- Rick
Nonsense. It just has to observe the setup and hold times.
Putting a DFF on the counter output and clocking it with the 10 MHz makes a crappy bang-bang phase detector, not a resynchronizer.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
LC
I am not so sure about that. It seems to me that you have used native LC tank phase noise when a forcing function version is more appropriate.
?-)
I have no idea what you are talking about. You seem to have a very different picture of what the correct circuit is than I do. I think we are not talking about the same circuits.
-- Rick
How so? I didn't mention phase noise, just tempco.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC Optics, Electro-optics, Photonics, Analog Electronics 160 North State Road #203 Briarcliff Manor NY 10510 hobbs at electrooptical dot net http://electrooptical.net
A 10EP52 does not have an enable input.
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
How do you plan to use the divided 80 kHz signal?
-- Rick
About like this:
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
*------------------ /1944 ->-|D Q|------|D Q|---| LOOP |----* | | | | | |FILTER | V *--^--* *--^--* *-------* | | | *------->-------* *---
So where is the output?
-- Rick
Where is the output?
-- Rick
Wherever I need it to be. What a PITA you are.
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
By using the divided clock to clock the reference you have added an unspecified delay which will vary with time, temperature, process and voltage. Is all this going to give you the 1 ps spec you need? Is there really no part available with an enable? That gets around the problem totally.
I realize now that whenever you get pushed into having to deal with problems you get angry and start insulting people. I'm sure that gets you miles with your coworkers.
I realize now why others have said this may stable in frequency but you can expect difficulties in phase. Or are you going to hand calibrate each one for the particular 10EP52 you use?
-- Rick
Find one.
There is no problem to deal with, except my unhappiness at running the sample loop at 80 KHz, which was the topic of this thread. I'll need a very good XO if the loop bandwidth is, say, 100 Hz or some such.
The question is meaningless. Just the coax from the GPS clock to my box will add nanoseconds of delay. What matters is long-term stability of timing, and low jitter, across the entire many-acre facility. Some of the gadgets that we'll be triggering are over 100 meters from this timing source. All the various electrical and fiberoptic and device delays have to be backed out to set the firing target times.
-- John Larkin Highland Technology, Inc jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Cool!
It might be interesting to try something like an SLA/AGM battery (Bleiakku), as found in computer UPSes, emergency lights, and so on. I bet the good ones would do about as well as the NiCd cells you tested.
Would the material/plating of the battery holder contacts affect the amount of noise you get? You might be making a thermocouple, or another little battery, at the connections.
Matt Roberds
What is the 1 PPS for? I must have missed that message.
On a sunny day (Mon, 15 Sep 2014 00:30:25 +0200) it happened Gerhard Hoffmann wrote in :
Cool, yes I also noticed some extra noise from eneloops (AAA). Nicads.. I still have one.
On a sunny day (Sun, 14 Sep 2014 18:30:16 -0700) it happened John Larkin wrote in :
You Romulan!
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