33 discussions on ElectronDepot about the Xilinx XC9500: what owners asked, what went wrong, and what fixed it.
I am very impressed. I was reading about Antti's incredibly tiny FPGA project board and saw a mention of a FOSS FPGA toolchain. Not just the compiler, but the entire bitstream generation! Several people have built on each other's work...
I want to put my latest idea in a PLD to save board space.Years ago I was comfortable working in PALASM, CUPL and ABEL.I also documented another guy's Verilog source.I see that Xilinx offers their ISE WebPACK suite for freebut it is said to...
Hi,I need to design an AM transmitter as a vlsi project (it needs to belocated on smart dust later on).Does anyone have any good suggestions were to start from? I am familiarwith vlsi, but don't really know how to implement such a big idea,...
I know others here have to deal with long life time support of designs, and Ihave one where I ahev to also supply the tools (free or paid) so that customercan support in at least 10 years time. The trouble is the design necessitatesa...
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HiI wonder if Xilinx does any testing of their releases at all - creating HardMacros seems to be impossible in 7.1 as the FPGAeditor self terminatesitself on any attemp to add extpin. Well it seems to be that 6.3 made hardmacros are...