ðÒÉ×ÅÔ Michael!
21 Jan 05 22:38, Michael Serebrov -> All:
MS> íÏÖÅÔ ËÔÏ ÍÏÖÅÔ ÐÏÄÓËÁÚÁÔØ ÍÏÖÎÏ ÌÉ ÎÁÇÒÕÚÉÔØ ÓÁÂÖÅ×ÕÀ ðìéó ÏÄÎÏ×ÒÅÍÅÎÎÏ MS> ÎÁ 50 Ó×ÅÔÏÄÉÏÄÏ× Ó ÚÁÄÁÎÎÙÍ ÔÏËÏÍ 10ÍÁ ÎÁ ËÁÖÄÙÊ. ÷ ÄÏËÕÍÅÎÔÁÃÉÉ ÎÁ MS> ÎÅÅ ÎÁÛÅÌ ÔÏËÁ ÞÔÏ ËÁÖÄÙÊ ×ÙÈÏÄ ÍÏÖÎÏ ÎÁÇÒÕÚÉÔØ ÎÁ 25 ÍÁ ÎÏ ÎÉÞÅÇÏ ÎÅ MS> ÎÁÛÅÌ ÐÒÏ íáè ÓÕÍÍÁÒÎÕÀ ÎÁÇÒÕÚÏÞÎÕÀ ÓÐÏÓÏÂÎÏÓÔØ. ÎÁÇÒÕÚÉÔØ ÎÁ - ÎÅ ×ÙÊÄÅÔ, Á ÏÔÂÉÒÁÔØ ÏÔ ÎÉÈ ÔÏË..
VOH Output high voltage for 5 V operation IOH = -4.0 mA /VCC = Min - 2.4 V Output high voltage for 3.3 V operation IOH = -3.2 mA /VCC = Min - 2.4 V VOL Output low voltage for 5 V operation IOL = 24 mA /VCC = Min - 0.5 V Output low voltage for 3.3 V operation IOL = 10 mA /VCC = Min - 0.4 V
ðÏ ÐÅÓÓÉÍÉÓÔÉÞÎÙÍ ÐÒÏÇÎÏÚÁÍ
0.5
*0.01*50=250mW × ÄÏÐÏÌÎÅÎÉÅ Ë ÏÓÎÏ×ÎÏÍÕ ÒÁÓÓÅÑÎÉÀ.
ðÏ ÏÐÔÉÍÉÓÔÉÞÎÙÍ (for XC9500 CPLD)
12*0.01^2*50=60mw..
MS> ÷ÓÅ Ó×ÅÔÏÄÉÏÄÙ ÍÏÇÕÔ ÇÏÒÅÔØ ÏÄÎÏ×ÒÅÍÅÎÎÏ É ÎÅÏÇÒÁÎÉÞÅÎÎÏÅ ×ÒÅÍÑ ... HÏÒÍÁÌØÎÙÅ É ÐÒÉ 5-8Íá "ÄÉÅÔÅ" ÓÉÑÀÔ ËÁË ÅÌËÁ.
in addition:
CMOS I/O Characteristics by PETER ALFKE u ( snipped-for-privacy@xilinx.com) xcell28
This article will give you an overview of our device I/O characteristics, to help you create better, more reliable designs. All Xilinx devices use CMOS technology,
which means there are two types of transistors: ÄN-channel transistors, turned on by a positive gate voltage. ÄP-channel transistors, turned on by a negative gate voltage.
For either transistor, the turn-on voltage must exceed the ~1-V threshold voltage. Figure 1 shows a complementary inverter, consisting of a p-channel pull-up transistor and an n-channel pull-down transistor with both gates driven in common. Outputs All Xilinx devices, except for the XC9500 family and the original XC4000 family, have complementary outputs. However, for XC4000E, XC4000EX, and Spartan families, you must specify this option explicitly. The default on these devices is _TTL output_ as described below.
Complementary outputs (See Figure 1.) are pulled _rail-to-rail,_ maximizing the output swing, especially desirable when driving other CMOS logic. With no DC load, the output voltage swings precisely between ground and Vcc with no voltage drop (the device output specifications of 0.4 and 3.86-V refer to particular dc loading conditions).
_TTL outputs_ (See Figure 2.) have a reduced voltage swing, which achieves faster performance, especially for the High-to-Low transition when measured at the usual 1 .5-V level. The term _TTL output_ is actually a misnomer, derived from the similarity with the _totem-pole_ structure of bipolar TTL outputs that use only npn transistors for pull-down and pull-up. Similarly, the _TTL output_ structure in CMOS uses only n-channel transistors output High voltage (Voh) by one threshold voltage, (1 to 1.5-V) below Vcc. At 3.3-V supply voltages (and lower), complementary _rail-torail_ or CMOS is the only available (and meaningful) output option.
The output impedance for our FPGAs is 15 to 30 Ohm in the Low state, and 30 to 50 Ohm in the High state. The output impedance for our /XC9500 CPLDs/ is t 10 o 12 Ohm in the Low state, and 70 to 120 Ohm in the High state The XC9500 and the original XC4000 devices have TTL-level outputs only.
On XC4000E, XC4000EX, and Spartan devices, TTL-output is the default, but can be changed to complementary output. If any data sheet specifies VOH as >3.5-V, it is a complementary output. If VOH is specified as 2.4-V, it is a TTL-level output.
Note that an output driving a long interconnect line or PC board trace can see reflections that drive the output well above Vcc and well below ground. Such reflections usually last for just a few nanoseconds (<10 ns) and are usually suppressed by the Continued on Figure 1. Complimentary Inverter or Buffer. Figure 2. Totem-Pole _TTL Output_ Buffer
Vitaly Polikarpov, vitvp[Üt]mail.ru