Anyone here have any information they can offer about basic FPGA starter kits?. I'm not after anything spectacular to begin with but after the last trip to DSE trying to buy 74 and 4000 series logic, I figure now is the time to learn and I have a nice project to implement where space is critical.
To replace 74 and other logic, cplds would be a better match complex programmable logic devices.
For larger amount of logic fpgas.
Problem you will have is the device voltage levels. very little works at 5v and are expensive, most are 1.8 or 3.3V so you will still need some 74 chips for interfacing 74hc125 , 74hc244 etc
Altera and Xilinx are the larger two suppliers and the ones I'm familiar with. Lattice also makes fpgas and cplds. Theier Machxo chips look quite interesting.
Both xilinx and altera have starter kits from US$49.
Both have free versions of the software that you can download if you have a fast connection - at least 1GB download.
Will need a few GB's free on your hard drive. Programs can crash or be buggy especially xilinx.
Altera has much better support for schematics (design by schematics). Both support hdls (hardware description languages) - vhdl and verilog.
If you can, I'd recommend taking the time to learn an hdl, would give a lot more flexibility and power as well as future proofing your designs compared to schematics.
I'll put the Altera kits I have links for, in a seperate post.
Xilinx fpga kits start at around US$149 , cpld kits from US$49 They are pretty good. Fpga starter kits S3 , S3e , S3a and S3an. Made by digilentinc.com for xilinx. S3e is the one you should look at.
Either of the cpld kits is pretty good.
try to get a kit using usb port for programming
coolrunner 2 starter kit US$49
coolrunner2 addon peripheral kitgoes with starter kit US$99
cpld design kit
I've used a few of these - easy to use (once familar with software)
s3 - main stream / value range compared to virtex2 pro, virtex4 and virtex 5 series s3e - economy s3a - economy/lower end part - less features s3an - flash memory builtin
S3e starter kit - US$149 (also used one of these)
3a starter kit - US$225 (just recieved one of these - just opened it this morning)
s3an starter kit - US$225
Looking at getting one of these for a project I'm going to be starting on soon Spartan-3 PCI Express Starter Kit (HW-S3PCIE-DK) - US$349
Can buy all these kits from Avnet in Australia but are usually slow, 6 - 16 weeks for delivery in my experiance. Buying direct from digilent is faster but shipping last time I ordered from them was quite expensive but had the boards within 4 days.
Xess also make a few xilinx boards from US$89 upwards.
Have some good tutorials
here in Sydney sell an fpga board. we use them in the remote student labs at work(UTS).
UTS sells a kit to its students for Introductory digital systems for microchip pic and xilinx cplds for around $100. Takes about 4 - 10 hours to solder it up.
Hi Alex, my current prototype uses a 3.3V I/O 20 MHz 16 bit RISC processor but it does occasionally miss a few pulses at high speed as it stops to convert and display the result to an LCD. I thought if I use a hard wired logic circuit I can solve the problem completely.
Thanks Alex, that'll take some time to digest, at this point I'm tending towards the Xilinx 9572XL series but I'll have to look at the others a bit more first. The Xilinx seem to be pretty good value from Avnet
msp430 ? Using interupts ? More efficent way of coding the conversion ? lookup table ? What about using a second slave micro conected via spi? You already have the tools and are used to using them.
Depends on what you want/requirements.
A larger / faster micro maybe cheaper than adding a cpld.
If its just a simple quadrature decoder circuit with a serial shift register output of a binary up/down counter. You maybe able to replace the micro with a cpld.
Should be able to get a much higher speed with the cpld but you will have the additional learning curve of the software and hdl.
You should be able to get the xilinx xc9572xl's in plcc44 for around US$2 each if you buy enough(last time I purchased approx 60 ) Can also get plcc84 packages. Seem to be a lot more expensive now than six months ago.
Small fpgas are cheaper than the mid size cplds have a look at the thread in comp.arch.embedded on serial cpld especially the posts by Antti and Jim Granville.
Only for the LCD routine, there's a timer interrupt every 3/4 of a second or so. The A and B encoder lines are continuously polled in an endless loop and if I get a result that indicates a missed increment say 1,1 to 0,0 I look back to the previous change to determine if it's up or down and then increment or decrement by 2 accordingly. It's fast enough if you don't manually flick the encoder shaft fast up and down repeatedly.
I threw away the "encoder counter to degrees" conversion routine to reduce code size and write the encoder binary data directly to LCD registers using the routines below:
The extraction of each individual decimal digit from the 16 bit binary count relies on a modulus by a power of ten to remove the digits above the wanted digit then a divide by a power of ten to reduce the digit to a value between 0 and 9 including decimal places which I then trim by saving into an integer.
I'm using the hardware multiplier as much as possible: a multiply by a reciprocal- A * 0.1, instead of A / 10 saves about 30 bytes at compile time, I'm assuming because the compiler does the divide in code
So the conversion uses a modulus and a multiply to get each of the five digits which are then converted to seven segment form with an array look up to return a byte to write to the LCD I/O register.
By setting the compile time options to "fastest" and turning off all debug options I get the code down from 2200 odd bytes to below 600 bytes and still have the very occasional problem that may not affect the production units as I doubt you could spin them that fast due to physical mass considerations.
I'm going to use the LSI LS7366R to start with: it's a 4X quadrature decoder /binary counter IC with SPI interface. After that I'll have time to build a simple logic 4X quadrature decoder circuit in logic gates to interface with the micro's hardware up/down binary counter. Either option would then have the micro only handling the conversion of the binary value to seven segment LCD.
One solution that just occurred to me is that I can detect when the encoder is stationary and then and only then, run the LCD update: this may entirely fix the problems.