CPLD beginner questions

I'm currently using GALs (16V8-18V8-22V10), but my current board requires 4 GALs and I would like to replace them with one CPLD which would also replace 4 other general ICs.

I've never had the guts to try CPLD because I thought they were complicated to learn, hard to solder and most of all, impossible to programm without some $$$.

Now I think different, but am unsure...

I've choosen xilinx's XC95-36-72-108 to work with.

I've read some examples of VHDL and I think it suits me. Non-SMD PLCC socket will make it easy to solder.

Now, programming..

Is it true that all I need is a FREE Webpack software and a simple JTAG cable???

Will the Webpack only produce the fusemap or does it also contain the software to actually burn the chip? If the burn software is not contained in the Webpack- where do I get it from? Or that is where the $$$ comes in?

Current version of Webpack is huge for my modem (2.25Gb) but maybe I'll get the version 7.1i - what do you guys think of that version with XC95-36-72-108 in mind?

The last question (for now, sure) is: how are CPLDs programmed, with JTAG or something else?

Everybody says that it uses JTAG, but I've found a PDF that says different: google for "XILINX PROGRAMMER QUALIFICATION SPECIFICATION"

That PDF is using address bus(A0-A13), data bus(D0-D3), and several signals (TSTEN, PGMEN, VFYEN, TS0-TS3, AD_STB) to burn the XC9500 family.

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Welcome ;)

I have never done CPLDs (I went straight from 74HC to FPGAs lol) but CPLDs are similar (simpler) and it isn't that hard if you have the hardware mind.

When I say it's simple, I mean once you learn the tools, doing simple things is simple, solving a hard problem is still hard of course, but having infinite reprogrammability still makes it much easier than doing board respins !

It's interesting and you'll probably enjoy learning that stuff.

Go for it, the investment is small...

Try Verilog and VHDL and choose according to your taste.

Yes. The JTAG cable must be Xilinx-software-compatible though, don't use a JTAG cable for ARM or something.

It contains all you need including the free simulator which will allow you to check your design before burning the chip.

Before you build any hardware you should install the software, implement your design, and simulate it thoroughly. Always test your pin allocations BEFORE manufacturing the PCB ! The synthesis tool will tell you if you want to use an impossible pin mapping.

Get it on DVD, or have a friend download it with DSL...

Get the latest versions, less bugs, smoother user interface, etc.

You are not going to want to take the chip out of the circuit to place it in a programmer every time you want to experiment so you are going to use in-circuit programming which means JTAG.

RTFM, lol, datasheet page 13 states :

XC9500 devices are programmed in-system via a standard

4-pin JTAG protocol, as shown in Figure 13. In-system pro- gramming offers quick and efficient design iterations and eliminates package handling. The Xilinx development sys- tem provides the programming data sequence using a Xilinx download cable, a third-party JTAG development system, JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. All I/Os are 3-stated and pulled high by the IOB resistors during in-system programming. If a particular signal must remain Low during this time, then a pulldown resistor may be added to the pin.

External Programming

XC9500 devices can also be programmed by the Xilinx HW130 device programmer as well as third-party program- mers. This provides the added flexibility of using pre-pro- grammed devices during manufacturing, with an in-system programmable option for future enhancements.

Use JTAG. But (as mentioned on this list a few days ago) be extremely cautious about the signal integrity of the TCK signal. Try to get an example reference design schematic and work from there.

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What do you program the GALs with now ? - many pgmrs also pgm CPLDs (so you just need an adaptor)

Or, you can use the JTAG ISP

There are also Atmel ATF150xASL series, in PLCC, but lower power than XC95xx.

Note that PLCC is now somewhat trailing-edge, and newest families are TQFP only.

This does show a problem with Tools. Those that bundle FPGA+CPLD, can get code bloat.

Some vendors separate out the download, to allow CPLD users to avoid the pain of GB's.

You could look at Atmel's WinCUPL - very fast compile of easy to use boolean equation entry - fine for spld merge tasks, and for most 32/64/128MC CPLDs.

WinCUPL is a small 21MB (even smaller as command line model only), and you also need ATMELISP v6.4 @ 2MB to pgm the JED file (that model uses a parallel port SW JTAG )

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WinCUPL also has a functional simulator, that can append JED test vectors, which allows Programmer verification of operation (in a ZIF style device programmer)

Lattice and Xilinx also allow you to code in ABEL, which is easier to learn than VHDL.

Check the device pinouts - if they have TMS/TDI/TDO/TCK, then it is JTAG.


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Jim Granville

Note also that XC95xx has smaller logic operation capabilities against XC95xxXL or XC95xxXV and has higher prices.

Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Uwe Bonnes

The XC95xxXV (2.5V device) states this :

Xilinx Data Sheet: [Note: This product is being discontinued. You cannot order parts after May 14, 2008. Xilinx recommends replacing XC9536XV devices with equivalent XC9536XL devices in all designs as soon as possible. Recommended replacements are pin compatible, however require a VCC change to

3.3V, and a recompile of the design file. In addition, there is no 1.8V I/O support.]

- seems 2.5V never hit critcal mass, and thus is EOL....

As Uwe mentions, the XC95xxXL is MUCH cheaper than the XC95xx, BUT the XL is a 3.3V VccIO device.

The ATF1502ASL is 5V Vcc capable - that may matter, when replacing SPLDs.

Some of the new Lattice devices mention 5V tolerant IO (when VccIO=3.3V), but they are not in PLCC packages, and still need multiple Supplies.


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Jim Granville


>    Welcome ;)

Thank you!
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aleksa wrote: PFC

Not all pins are created equal. Global CLocks, Global OE, Global CLRs are typical, so those have obvious natural allocations.

Then, if a design gets full, you can find some CPLD resource limits free placement of all I/O - so it is always a good idea to both fit First, and also read the Fitter .RPT files, to see the Logic usage, and how much head-room you have.

Also feel free to trial intermediate nodes : sometimes having' them gives a smaller desigm, sometimes allowing the fitter to collapse them, can give a smaller design. (but still readable at the source level)


Reply to
Jim Granville

Then your brain is wired for hardware ;) good for you !

Not necessarily, also, some have special functions that you might want to use. Also, voltage and banks come into play.

If you're in Euroland, could try Olimex, they are very cheap and I heard recommendations for them :

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If you have $50 to experiment the Digilent kit includes a simple JTag cable and a nice board with two CLPD devices. An XC9500XL and a Coolrunner II. It operates on two AA Batteries or an optional wall-wart. (Or your own bench supply) The ISE CD is includes as well as a reference VHDL design with a simple counter and button de-bounce ckt. You can download the design and other info about the board at the link below.

If you like I believe you can do your design in schematic form and in the case of a small design this may be all you need. The built-in ISE tools have core builders for many functions with a wizard-like menu to build more complex logic blocks. If you are just starting you may want to consider Verilog over VHDL. (seems to be more common in the market today)

The nice thing is you get the instant gratification seeing your design work (not waiting for a asic build or board design) and you can make mods and improvements quickly. (Just re-program the chip)

The ISE package includes the "impact" software to load/erase/re-load the device. This can also be run from the command line (and they support Linux) You can download the lab-pack that just has the impact part of the toolset if you need just that piece (ie in the lab where you don't want to install the full design system). This is all free for the CPLD's and the smaller FPGA's

7.1 should be fine for the CPLD family. Make sure you update with the latest service pack.

JTAG seems the easiest with the toolset. With JTAG you can target any one device in the chain (ie if you have multiple CPLD's or a mix of JTAG compatible parts on your board) through one connection. Some of the newer devices can also be programmed with a SPI (serial interface.) (ie Spartan-AN that now has non-volitial flash load) I think I saw the option on some of the Coolrunner parts but I cannot recall. I have also done bit banging on the FPGA parts (Done,CLK,D0in,PROG,and one more I can't recall INIT maybe) through the load pins. I have not tried the procedure you showed above on a CPLD.

CPLD Design/Development kit from Digilent: (They build many kits for Xilinx parts)

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Have fun, Bart

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The XC95xxXL CPLDs do indeed use 3.3v VCC, but their I/Os are 5v tolerant. However, an output's HI is 3.3v, not 5v. If you are using

5v TTL (i.e. 74LSxx) or 5v CMOS with TTL input thresholds (i.e. 74ACTxx), then you can use a XC95xxXL CPLD. Otherwise you'll need a 5v device (XC95xx). I've used both 5v devices (XC9536 & XC95108) and 3.3v devices (XC9572XL), with both 74LS and 74ACT chips. HTH

-Dave Pollum

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Dave Pollum

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