ISE/EDK 6.3 vs 7.1...

This maybe an issue with the constraints listed in the UCF file.

iSE 7.1 incorrectly interprets "NET-PERIOD" constraints when applied to designs assembled from multiple NGC files. Unfortunate, as this is the design assembly method of EDK.

If you have a UCF constraint of the following format:

NET sys_clk PERIOD = 10 ns;

Replace with the following

TIMESPEC "TS_sys_clk" = PERIOD "sys_clk_grp" 10 ns; NET sys_clk TNM_NET=sys_clk_grp;

Also, you may want to also change the effort level of "-ol std" to "-ol high". This can be modified in the /etc/fast_runtime.opt

Big Boy wrote:

I also noticed that the fitter for ISE 7.1 isn't as efficient. I had a legacy design for an XC9500, and I called Xilinx tech support on an unrelated issue. I was using 6.3, the tech support guy used 7.1, and he couldn't fit my design to the chip. He had to install 6.3 to be able to work on it. It really does seem that the new fitter isn't as efficient.

design for an XC9500, and I called Xilinx tech support on an unrelated issue. I was using 6.3, the tech support guy used 7.1, and he couldn't fit my design to the chip. He had to install 6.3 to be able to work on it. It really does seem that the new fitter isn't as efficient.

What puzzles me is WHY they would change the 9500 fitter between 6.3 and 7.1 releases. Surely the 9500 qualifies as ancient/'highly stable' ? ie Was there a reason for the change/fit failures ?

-jg

The 7.1 does generate a correct UCF file and constraints. The proble seem related to the ISE tools, which synthesize ro translate to larger design, with deeper level of logic

I also tried different level of effort. This helped, but still doe

not get as packed as ISE 6.3 tools

Maybe a newly implemented algorithm need some tweeking

Thanks for the answers, so I'm not the only one having those issues

Hit a good one with 6.2 and 6.3 when using schematics with xc9572xl making your own xor takes up less space than the builtin xor.

Haven't tried it with 7.1 yet.

Alex

I have similar problems with the (official) ML40x reference design and the EDK

IMHO, for XC9500 CPLD's it is best to stick with Webpack 5.2. Only yesterday I had a case where I needed to modify an old design slightly and in this occasion I thought to migrate the design to the lastest ISE version. The design failed to work, but in a way that only some signals were wrong. So the failure was not noticed immediately, since some parts of the design worked, but an important function did not. Simply compiling the design with 5.2 brought the design to work.

Since this was not the first time I got burned with

The story however confirms my opinion that the XC9500 family is a unloved child in Xilinx.

Regards Klaus

XC9500 is not Xilinx child, they did buy the technology in... same as they did buy CoolRunner, to my knowledge Xilinx has no own PLD technology at all.

Antti