LVDS in Xilinx (Spartan-3)

Yup, that is a big difference. 2 KV of HBM ESD is really not very robust at all.

My only experience is 5V Spartan FPGAs and XC9500 CPLDs. I have ONE customer who has blown up DOZENS of Xilinx parts. I have never been to his location, I'd like to find out what he is doing to cause this much damage. I have never had a field failure with any other customer. The product consists of several boards, one FPGA or CPLD each, that plug into a backplane. In another related product that puts much of that function into one larger FPGA, I went to the trouble of adding a bunch of Littelfuse SP720AB ESD suppressor arrays. I get them from Digi-Key, with 14 protected lines for $2.82 in quantity of 10. All I can say at this point is they don't affect the operation of the circuit. They do spec a low capacitance.

I have had a few strasnge Xilinx incidents I can comment on. Once, in the winter, I was working on a board with an XCS10-3PC84C FPGA, and as I sat down, I touched the board. Sparks shot all over it, I am positive I saw at least 5 separate sparks, 4 of them jumping between pins on the board, and one from my finger! The board was powered on at the time, which may be relevant. That board is still working today!

Another time, on the "related" product mentioned above, with an XCS30-4TQ144 FPGA, I had just assembled the board, powered it on, checked that it configured correctly (I have a RED LED that lights and goes off when the config completes OK) and then powered it off, to connect it to test gear. When I applied power again, it did not power up. The chip was shorted, and when I applied an external bench supply, the chip was drawing 1.8 A. I replaced the Spartan, and it worked fine. I was not aware of any particular thing that happened that could have caused an ESD event.


Reply to
Jon Elson
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Hello all,

I am considering using the LVDS mode in spartan-3 FPGAs to run offboard via a cat-5 RJ-45 connector. We have been doing this for a long time with LVDS parts from TI and National, but using the FPGA directly would be a cost savings (but also require a lot of pins!)

I am concerned about exposing these I/O pins this way, I feel much safer with the layer of protection the LVDS parts put between the FPGA and the outside world. I have no doubt that these parts are safer, but do I need this? Most Xilinx parts claim a 2kV ESD spec, human-body model, whereas the LVDS components spec 20kv. Or maybe I would need to diode-protect these (expensive).

Does anyone have any advice, or has anyone had any good or bad experiences doing this? Along these lines, what do you recommend to protect any exposed FPGA pin? We usually try to avoid them, but otherwise we will use series resistors and diode protection depending on the application.

Thanks! Jason Daughenbaugh

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Reply to
Jason Daughenbaugh

Consider that a customer may plug your RJ-45 into an ISDN socket with 100V DC across some of those pins.

Look at at some ethernet phy app notes.

-- Mike Treseler

Reply to
Mike Treseler

Don't quote me on this, but I seem to remember that CE required a 15KV human body model - you might look it up just to make sure, but if you plan to ship to the CE, you'll need this.


Jas>Hello all,

Reply to
Andrew Paule

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