CPLD HDL?

I want to put my latest idea in a PLD to save board space. Years ago I was comfortable working in PALASM, CUPL and ABEL. I also documented another guy's Verilog source.

I see that Xilinx offers their ISE WebPACK suite for free but it is said to have 'limited' simulation ability. There are addon$ available that have complete simulation ability.

My Question Without Intending To Start A Religious War:

What modern HDL compiler and simulator package has: The ability to run on Linux A gentle learning curve Good user support Fast, easy use Efficient use of PLD resources Support for multiple part vendors Reasonable purchase price ..and all other characteristics of a superior product. :)

Thanks!

--Winston

Reply to
Winston
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as far as I remember the limits is that with more than 1000 lines of code simulation gets slowed down, and code for xilinx blocks doesn't count, Not a big problem with a cpld sized design

you could always use a free simulator like e.g Icarus and GTKWave

don't know if multiple vendor is really available

-Lasse

Reply to
langwadt

OK. Thanks!

--Winston

Reply to
Winston

I run the free webpack version on some systems, the "limits" have never bothered me, I use modest FPGAs and CPLDs. Runs well on Linux. The only thing I know doesn't work is printing schematics, which I don't use much, anyway. CPLDs will not have very big HDL files, maybe 1-2 pages. I use VHDL, you can also use Verilog. Hmmm, not so sure about user support. You get email support with the free tools, and phone support with the paid tools, but their phone support is pretty awful, or was the last few times I called. I ended up diagnosing the problems myself and telling THEM how to fix it! I think the efficiency is good but have nothing to compare it to. But, expensive packages use Xilinx back-end tools to do place and route. Obviously, Xilinx tools don't support other vendors.

Jon

Reply to
Jon Elson

Thanks, Jon.

Sounds like I ought to contemplate a microcontroller implementation instead. Then I could use assembly, which I find entertaining.

--Winston

Reply to
Winston

Oh, don't give up now, I was hoping to harvest ideas from this thread for a board that's already got four 74AHCxx parts on it, and seems to be acquiring more!!!

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Reply to
Tim Wescott

I use Xilinx' free webpack for their CPLDs. Their XC9500 series is pretty cheap. As a language I use VHDL because... I know VHDL. For simulation I use ghdl (ghdl.free.fr).

Not on this world...

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Reply to
Nico Coesel

Well, I do a lot of stuff where micros may be too slow, or not parallel enough. VHDL is pretty easy to pick up. And, you CAN enter a schematic, even in familiar 74xx part numbers, wire it all up and have it turned into logic on a CPLD or FPGA. Some interface glue projects I still do it that way, although I am moving more and more to HDL.

Jon

Reply to
Jon Elson

CPLDs have really saved the day sometimes when working with the ASICs we make, and we find some dumb error in the ASIC. Well, just throw some more gates into the CPLD and fix the goof. The Xilinx 95xx series is still available and runs off 5V, too! (Warning, the power consumption given by their formula is WAY optimistic, it can be 3X higher than they claim.) Xilinx admitted this in email, but refused to correct the docs.

In power-sensitive applications, the Cool Runner II is a MUCH lower power CPLD, but it is 3.3 V only.

Jon

Reply to
Jon Elson

Oh, note that due to export restrictions, the free webpack will not run on 64-bit OS's. Apparently you can alter some links to 32-bit libraries and make it work.

Jon

Reply to
Jon Elson

I haven't done a PLD in quite awhile--my current toolset is Orcad PLD for DOS. ;) They're great for stuff where you need better timing coherence than the processor can give you, e.g. sampling.

What's the easiest way to start with VHDL?

Cheers

Phil Hobbs

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Reply to
Phil Hobbs

Tim > Oh, don't give up now, I was hoping to harvest ideas Tim > from this thread for a board that's already got four Tim > 74AHCxx parts on it, and seems to be acquiring more!!!

Jon, Tim and I would very much like to know what package you use to capture a schematic and output (JEDEC?) for a CPLD or FPGA. Is the ghdl package Nico mentioned involved?

Thanks

--Winston

Reply to
Winston

Fortunately Linux doesn't need 64 bit to use >3GB of memory :-)

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Reply to
Nico Coesel

I guess a good book with actual examples, not just a language specification :-) Just make sure it covers writing functions and so on. There is a lot of power in VHDL. In the past I've often designed pieces of logic which can be configured for different widths, channels, etc. That took some studying to get it right but it has paid off big time in several occasions. It helps if you have a programming background.

There is also Verilog but I never understood Verilog. It makes me feel like I'm looking at a netlist output from a schematic.

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Failure does not prove something is impossible, failure simply
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Reply to
Nico Coesel

Is there an equivalent to K&R for VHDL?

Cheers

Phil Hobbs

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Reply to
Phil Hobbs

I use Xilinx Webpack on Linux, and the Icarus Verilog simulator.

Gentle learning curve just doesn't apply to Xilinx software.

I suppose support is good if you use Xilinx or Altera, between the USENET and manufacturer forums. I rarely need support, and even when I do it's just to save some time rather than figure it out myself.

I've never taxed any of my PLDs enough to care about very high efficiency.

Support for multiple vendors? Well, that will only happen if you aren't using the software from one of the manufacturers. I don't go there, due to too high prices, which I prefer free.

Good luck and have fun.

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Mr.CRC

(...)

I see what you mean. I downloaded and installed just now. Holey Cannolli! In the Good Old Days, you just supplied a source file and told the compiler to get started. The tutorial has me doing all kinds of gyrations, referring to unlabeled windows and sending me on a goose chase to locate buttons that are not visible on the existing screen, all with no explanation of *why* these things need to be done. Wow!

Thanks, Mr. CRC

--Winston

Reply to
Winston

Hello - This thread is so Xilinx centric !

Have a look at Lattice - their free tool is based on Aldec HDl which is nice (Schematic, VHDL and Verilog in one simulator -I have the paid for version but the free one is OK for small stuff).

Lattice have a much better offering than Xilinx (IMHO) for small FPGA and PLD/FPGA crossover parts.

Michael Kellett

Reply to
MK

A generic tool that allows simulating VHDL is GHDL. I use it on linux, don't know if there is a windows port. HOWEVER, you have to be careful, as GHDL is a pure simulator and simulates exactly what you write (which is sometimes not what you want): if you forget to add a signal to the sensitivity list of a process, it will not react to changes in that signal. Altera's Quartus , for instance, defaults to implicitly add every signal you read inside a process to the sensitivity list (which is usually what makes sense for synthesis), giving you a warning. There are also constructs that are not synthesizable.

For instance, process(A,B) and process(A) are not the same if inside you want to achieve C

Reply to
o pere o

On a sunny day (Fri, 10 Feb 2012 01:19:52 GMT) it happened snipped-for-privacy@puntnl.niks (Nico Coesel) wrote in :

Verilog looks more sane to C programmers. It usually is less typing (I mean like hitting keys) work than VHDL, VHDL reminds me of ADA, and I threw away that book. So maybe if you come from a C background Verilog is easier to get used to. Somebody did a VHDL version of a camera software I did in C, and I could not read it... I found Verilog easy to learn. You were talking about crypto, I did a nice decoder for some well known TV crypto system in FPGA, to do it all with logic gates (one clock decoding), so they could brute force faster. That system is now longer in use for obvious reasons, Those were the times when hackers were still heros.. These days it would get you arrested, Actually published that code on the internet, may be it is still somewhere.

Reply to
Jan Panteltje

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